TSMC CoWoS Prices Could Rise 20% as AI Demand Pushes Equipment Waits to Eight Months

AI chip orders squeeze packaging and equipment supplies

TSMC is considering increases of 10% to 20% for its CoWoS advanced packaging services as demand for artificial intelligence chips strains production capacity, according to supply chain accounts dated October 27, 2026. Equipment deliveries have stretched from three to six months to six to eight months, slowing efforts to expand the factories needed to clear growing order backlogs.

The pressure reaches beyond graphics processors used to train and run AI systems. Server central processing units and custom chips are also competing for advanced packaging, while increasingly complex processors require more time on testing equipment. Chipmakers face a shortage of both assembly capacity and the machines needed to create more of it.

TSMC has reportedly changed its equipment purchasing approach in response. Suppliers say the company placed orders at existing prices this year without its customary requests for discounts or extra features at the same price. For equipment makers, securing delivery dates has become more important to customers than negotiating a cheaper purchase.

The proposed packaging increase remains a supply chain expectation, with no confirmed starting date or detailed customer price schedule. The figures circulating for future capacity are also analyst projections rather than a single published company commitment.

The central problem is that AI demand can grow faster than production lines can be built and qualified. Industry participants estimate that a new advanced packaging plant can take about three years from groundbreaking until its slowest processing stations operate at full capacity. Ordering more machines is only the beginning of that process.

Why packaging has become a constraint

CoWoS stands for Chip-on-Wafer-on-Substrate. It brings computing chips and memory together in a tightly connected assembly, allowing large amounts of information to move between them quickly. For powerful AI processors, that connection is a major part of how the finished product works.

Modern AI packages increasingly contain several computing dies, the individual pieces of silicon that perform calculations, alongside high bandwidth memory, or HBM. This memory supplies data rapidly so that processors can spend more time calculating and less time waiting.

More components mean larger packages and more complicated manufacturing steps. Equipment suppliers say larger assemblies can reduce the number of units a machine processes each hour. A factory may therefore need additional equipment simply to maintain its existing shipment volume as customers move to bigger designs.

Demand is also spreading across product categories. Graphics processing units, or GPUs, remain central to AI computing, but server CPUs and application specific integrated circuits, or ASICs, are adding orders. An ASIC is a chip designed for a particular task rather than a broad range of uses. These products widen the group of customers seeking access to the same specialist packaging resources.

Testing takes longer as processors grow more complex

Nomura Securities estimates cited in the reporting put final testing time for NVIDIA Blackwell chips at about four times that of the earlier Hopper generation. Rubin could require about seven times as long as Hopper. These estimates show why testing capacity is becoming a separate constraint alongside assembly.

Testing checks whether a completed chip functions as intended before it reaches a customer. When each unit occupies a tester for longer, the same equipment can clear fewer units in a working day, unless manufacturers change the process or add capacity.

Packaging companies consequently need to coordinate investment in assembly and testing. More output from one stage can leave a growing queue at the next if the equipment there cannot keep pace.

Foundries, which manufacture chips for customers, and outsourced semiconductor assembly and test providers, commonly called OSAT companies, are both facing this pressure. Industry accounts describe longer testing cycles as one reason providers are considering packaging price adjustments of 10% to 20%.

Delivery dates take priority over discounts

Equipment suppliers describe a marked change in negotiations with TSMC. In previous annual purchasing rounds, the company commonly sought a lower price or additional functions without paying more. This year, suppliers say it accepted existing prices without requiring extra capabilities.

For suppliers, that reduces the pressure to absorb the cost of discounts or additional engineering work. It can help preserve profit on orders, although producing and delivering the machines still depends on the availability of components and machining capacity.

Equipment delivery windows have moved from three to six months to six to eight months. The upper end has increased by two months, while the shortest quoted wait has doubled from three months to six. These waits concern production equipment; some packaging service delivery times have also lengthened, but no comparable range was given.

Upstream component suppliers and machining businesses are themselves operating close to capacity, according to industry participants. An equipment manufacturer accepting an order must fit its production schedule around those deliveries. A customer willing to pay the asking price may secure a place in the queue, but the machine still has to be assembled and prepared for use.

A completed factory still needs time to produce

Advanced packaging plants depend on a sequence of precise operations. Industry participants identify lithography, development and die bonding among the stations that can limit production. Lithography and development help create fine patterns, while die bonding places and attaches the individual chips.

The slowest stage determines how quickly work moves through the line. Improving one station can move the constraint to another, so expansion requires more than adding a single type of machine.

Equipment also needs adjustment and validation after installation. Engineers must establish settings that repeatedly produce functioning packages at an acceptable yield, meaning the share of output that meets requirements. A building with machines inside can therefore be months or longer away from its intended steady output.

The industry estimate of roughly three years from groundbreaking to full operation at key bottleneck stations explains why construction announcements and immediate supply relief can be far apart. Meanwhile, equipment waits of up to eight months limit how quickly existing facilities can add production tools.

Capacity forecasts point upward, but differ on scale

Analyst estimates accompanying the October 27 account put TSMC CoWoS capacity above 130,000 wafers a month in 2026, with a target of 200,000 a month in 2027. Other institutional estimates put capacity at 115,000 to 140,000 wafers a month by the end of 2026 and approximately 170,000 a month in 2027.

Goldman Sachs projects annual capacity of 1.275 million wafers in 2026, 2.73 million in 2027 and 3.48 million in 2028. Dividing those annual totals by 12 gives monthly averages of approximately 106,250, 227,500 and 290,000 wafers respectively.

The bank's annual figures imply an increase of about 114% in 2027 and another 27% in 2028. Its monthly averages and estimates for capacity at the end of a year measure different things: a plant starting production late in December adds little to that year's total, even if it raises the capacity available for the following year.

The forecasts still differ substantially for 2027, ranging from about 170,000 wafers a month to Goldman Sachs' annual average of 227,500. Customers planning chip launches face uncertainty about how much capacity will become available and when, even as every projection anticipates a substantial expansion.

Taiwan leads expansion as larger packages advance

TSMC's expansion plans include phased development of AP7 in Chiayi, equipment installation at AP8 P2 in Tainan, and additional SoIC capacity at AP6. SoIC is a related technology for integrating chips in three dimensions. The planned additions broaden advanced packaging capabilities across several sites rather than relying on one new factory.

CoWoS expansion is expected to be concentrated mainly in Tainan and Chiayi. Overseas plans include an American advanced packaging plant identified as AP1, with production planned for 2028.

TSMC Chairman and Chief Executive C.C. Wei has said CoWoS remains the preferred approach for customers. In remarks described from the latest earnings call, he said packaging at five times the reticle size was already in mass production with strong yields, while versions at nine and 14 times the reticle size were under development.

A reticle is the patterned template used in chip lithography. Here, multiples of reticle size express how large a packaging platform can be. Bigger platforms provide room for more computing dies and memory, but also increase the demands placed on assembly equipment and process control.

A reported development schedule points to 2028 for packaging at 14 times the reticle size. The aim is to accommodate larger AI systems within a package while expanding the production capability needed to manufacture them.

CoPoS introduces a different production format

TSMC is also developing Chip-on-Panel-on-Substrate, or CoPoS. Instead of using a circular wafer as the working format during packaging, the approach uses a larger rectangular panel. Its intended advantages include space for larger assemblies and more efficient use of processing area.

Rectangular panels could allow more packages to be processed in a production run and help reduce cost per unit. Large AI GPUs and custom ASICs are among the applications expected to benefit. Reaching those savings requires equipment, materials and processes that work reliably across the larger surface.

Supply chain accounts say major equipment installation for a CoPoS pilot line was completed in February 2026, with full line setup expected by June. Forecasts place the earliest mass production in 2028, while another expected window extends into 2029, followed by wider adoption.

CoWoS remains the main technology serving current demand while CoPoS develops. A related approach, fan-out panel level packaging, also uses panels, with applications including thin, densely connected packages for mobile devices, vehicles and connected equipment.

The initial CoPoS supplier list described in industry accounts includes Chroma ATE, Scientech, C Sun, GMM, APT, GPTC, Ta Liang Technology, V5 Technologies, Favite and Gudeng Precision. Their roles span processing equipment, inspection, automation, materials and carriers. Moving to panels therefore creates work across a broader manufacturing network, not just at the final assembly plant.

The dates and costs customers are watching

The packaging squeeze coincides with reported increases in the cost of manufacturing the chips themselves. TSMC has reportedly finalized wafer manufacturing price increases of 3% to 6% from January 2027, depending on the process technology, with 2 nanometer and 3 nanometer production facing the largest increases.

Chip manufacturing and packaging are separate parts of the production bill. A customer using an advanced manufacturing process and CoWoS could face higher charges at both stages. The reported percentages apply to different services, so the change in the finished product's cost depends on how much each service contributes to its bill.

The main milestones described by industry accounts and analyst forecasts are:

• February 2026: Major equipment installation for the CoPoS pilot line was reportedly completed, with full line setup expected by June.
• October 27, 2026: Supply chain accounts described potential CoWoS price increases of 10% to 20% and equipment waits of six to eight months.
• January 2027: Reported wafer manufacturing price increases of 3% to 6% are scheduled to begin.
• 2027: CoWoS capacity is forecast to expand substantially, although estimates differ on the scale.
• 2028: The American AP1 packaging plant is planned to start production, and a reported technology schedule points to packaging at 14 times the reticle size.
• 2028 to 2029: CoPoS could enter mass production under current industry expectations.

For chip designers and AI infrastructure buyers, the practical challenge is coordinating manufacturing, packaging and testing slots with product schedules. TSMC's investments address all three pressures indirectly through a larger production network, but equipment deliveries, process qualification and growing package sizes determine how quickly that investment becomes usable supply.

Key Points

• TSMC is reportedly considering CoWoS packaging price increases of 10% to 20%, without a confirmed implementation date.
• Production equipment waits have extended to six to eight months, compared with three to six months previously.
• Larger AI packages and longer testing cycles increase the equipment needed to maintain output.
• CoWoS capacity forecasts anticipate rapid expansion but differ substantially for 2027.
• Tainan and Chiayi are central to expansion, while the American AP1 plant is planned for 2028.
• CoPoS could support larger packages and lower unit costs, with mass production expected as early as 2028 to 2029.