TSMC Expands Advanced Packaging as AI Chip Demand Outruns Capacity

Larger AI packages, tighter capacity

TSMC is expanding the technology that binds AI processors and memory together, with plans for a packaging platform capable of integrating 20 high bandwidth memory components in 2028 and a version accommodating 24 in 2029. The targets show how the race for faster artificial intelligence hardware now depends on assembling larger, more complex systems, alongside making smaller transistors.

At the 2026 Taiwan Technology Symposium in Hsinchu on May 14, TSMC vice president for business development Yuan Li-pen announced mass production during 2026 of a 5.5-reticle-size Chip on Wafer on Substrate platform, known as CoWoS. He said its manufacturing yield exceeded 98%. Reticle size is a reference based on the area covered by a lithography exposure field, giving the industry a way to describe the scale of these increasingly large packages.

The expansion follows a warning from chairman and chief executive C.C. Wei during the April 16 earnings call that advanced packaging capacity was still very tight. TSMC expects its 2026 capital budget to approach the upper end of a $52 billion to $56 billion range, although that spending covers chip fabrication and other investments as well as packaging.

These developments expose a constraint that building more wafer factories alone cannot solve. Nvidia and AMD need both working processor dies and enough capacity to connect those dies to memory. A die is an individual piece of silicon containing a chip's circuits. Without the right package, even an advanced die cannot become a finished AI accelerator.

The capacity problem also crosses borders. Chips fabricated at TSMC's Arizona plant are still sent to Taiwan for packaging, according to reporting on its manufacturing network. Two planned Arizona packaging facilities could shorten that journey, but their completion dates have not been disclosed.

Why the package now shapes performance

For decades, semiconductor progress centered on putting more transistors onto a single die. Gordon Moore, an Intel cofounder, observed that transistor counts tended to double roughly every two years. Smaller transistors helped manufacturers improve computing performance and energy efficiency, but maintaining that pace has become harder and more expensive.

AMD and Intel began responding before the current AI boom by splitting large processors into multiple dies. Different functions could use different manufacturing processes, reserving expensive advanced technology for the circuits that benefited most. Smaller dies can also improve production economics because a defect need not spoil one enormous piece of silicon.

For AI accelerators, the immediate objective is often performance rather than simply reducing manufacturing cost. Powerful computing circuits need a continuous supply of data. High bandwidth memory, or HBM, uses stacked memory dies and many connections to deliver data quickly. Placing it close to the processor helps prevent computing resources from sitting idle while waiting for information.

Paul Rousseau, head of packaging solutions for TSMC North America, explained how CoWoS addresses that problem:

You just can't get enough memory inside your compute chip to fully utilize it. So when we introduce CoWoS, we are able to bring the HBM memory right beside the compute in a very efficient way,

CoWoS is described as 2.5D packaging because processor and memory components sit beside one another on an additional wiring structure rather than being connected only through a conventional circuit board. That structure, called an interposer, supports dense connections between the components. Packaging therefore becomes part of the processor's design, not merely a protective shell added after manufacturing.

Nvidia and AMD need different combinations

TSMC introduced its 2.5D packaging technique in 2012 and has developed successive versions. Nvidia's Blackwell GPUs use CoWoS-L, its latest generation discussed in the reporting. Nvidia has reportedly reserved a majority of TSMC's leading CoWoS capacity, making access to that specific technology a concern for other customers.

The progression from Nvidia's H100 to Blackwell illustrates why packaging matters even without a dramatic change in manufacturing node. H100 uses TSMC's 4 nanometer process and CoWoS with HBM supplied by SK Hynix. Blackwell uses the N4P process and HBM3e memory, combining changes in chip design, memory and integration rather than relying on transistor shrinkage alone.

AMD's MI300 takes another route. It uses TSMC's 5 nanometer and 6 nanometer technologies, with System on Integrated Chips, or SoIC, for vertical integration before CoWoS connects the assembly with HBM. This adds another advanced packaging stage to the manufacturing sequence.

The distinction matters when assessing shortages. CoWoS and SoIC perform different jobs, and expanding one does not automatically remove a constraint in the other. Customers also need the appropriate generation and package size, not simply access to an undifferentiated pool of packaging capacity.

Demand reaches beyond chip orders into actual computing installations. Foxconn's planned Taiwan supercomputing cluster, announced with Nvidia, carries a $1.4 billion investment and a target of beginning operations in the first half of 2026. Its planned Blackwell GB300 deployment illustrates how accelerator supply feeds into larger infrastructure schedules, although the announcement itself does not establish whether the facility has opened.

Rapid expansion has not removed the shortage

Rousseau put CoWoS capacity growth at an 80% compound annual rate. At the May symposium, TSMC vice president for operations and advanced technology engineering B.Z. Tien projected annual capacity growth above 80% for CoWoS and SoIC through 2027. These figures describe expansion rates, not proof that demand has been fully satisfied.

Earlier estimates show the scale of the buildup. CoWoS monthly capacity was estimated at 15,000 units in 2023, with forecasts of 45,000 to 50,000 by the end of 2024. That would represent three to roughly 3.3 times the 2023 level. The same reporting projected about 50,000 units by the end of 2025.

For SoIC, estimates rose from 2,000 monthly units at the end of 2023 to a projected 5,000 to 6,000 at the end of 2024, followed by 10,000 at the end of 2025. These were historical forecasts rather than confirmed production totals, and the unit counts should not be treated as a direct measure of finished accelerator shipments.

Reporting from that earlier period said Nvidia and AMD had booked CoWoS and SoIC capacity through 2024 and 2025. The stronger current evidence of continuing pressure is Wei's April 2026 statement that advanced packaging capacity remained tight despite expansion.

TSMC has converted older wafer facilities to packaging uses and is ramping two new packaging facilities in Taiwan. Its 2025 annual report commits to further investment in advanced packaging facilities at several locations in Taiwan over the next several years. The report identifies CoWoS, InFO, SoIC and Compact Universal Photonic Engine, or COUPE, among the integration technologies under development.

Taiwan remains central to the manufacturing route

TSMC's overseas wafer expansion does not yet provide a complete local manufacturing chain for advanced AI chips. Reporting on the company's packaging network says chips made in Arizona still travel to Taiwan for that stage. The planned Arizona packaging plants would address a missing capability rather than duplicate an established local service.

Jan Vardaman, a packaging researcher at TechSearch International, said placing packaging near the Arizona wafer factory would reduce turnaround time by avoiding shipments back and forth between Asia and the United States. TSMC has not disclosed when those packaging facilities will be completed, so the benefits cannot yet be assigned a firm start date.

The wafer expansion schedule is more specific. In its April earnings transcript, TSMC said a new 3 nanometer fab in Tainan would begin volume production in the first half of 2027. Arizona's second fab is scheduled for the second half of 2027, and Japan's second fab for 2028.

TSMC is also converting 5 nanometer equipment in Tainan to support 3 nanometer production and managing flexible capacity among its N7, N5 and N3 processes. Those measures increase wafer output, but finished AI hardware still requires the corresponding packaging and memory supply. Expanding each stage on a compatible schedule is therefore central to delivering usable products.

Larger packages bring harder engineering problems

The next CoWoS platforms aim to connect more computing silicon and memory within a single assembly. Yuan said the 2028 platform would reach 14 reticle sizes and integrate 20 HBM components, with a version supporting 24 planned for 2029. Those are development targets, not capacities already available to customers.

Yield is an important measure because it describes how much production meets the required standard. Yuan's reported figure above 98% applies to TSMC's 5.5-reticle-size CoWoS technology. Reports also put Intel's EMIB-T yield at about 90% and Samsung's 2 nanometer process yield in the middle of the 50% range. These figures do not form a valid direct ranking: they concern different technologies, and Samsung's figure concerns transistor fabrication rather than packaging.

Wei identified mechanical stress, warpage and thermal limits as challenges in larger packages. Warpage means an assembly bends away from its intended shape, potentially making precise connections harder to maintain. Thermal limits concern how much heat the system can generate and remove while operating reliably.

TSMC is also developing Chip on Panel on Substrate, or CoPoS. Wei said the company had built a pilot line and expected production a couple of years later. He made clear that large CoWoS packages remained the main supply approach at the time of the April call. A pilot line allows a company to test manufacturing methods before committing them to broader commercial production.

Stacking adds another route, with a timing caveat

Vertical integration takes the idea further by placing dies above one another. TSMC calls its technology SoIC, while Intel's discussed approach is Foveros Direct. Shorter connections can allow closely linked components to operate more like a single chip, although stacking also makes heat management and assembly more demanding.

Reports differ on the timing of SoIC products. Rousseau described products using the technology as likely a couple of years away, while the earlier account of AMD's MI300 identifies SoIC as part of its manufacturing process. The broader statement should therefore not be treated as a date for SoIC's first commercial use. It may concern upcoming applications, but its scope was not specified.

Memory manufacturers Samsung, SK Hynix and Micron already use vertical stacking in their own HBM manufacturing. That is distinct from stacking computing dies, even though both rely on advanced assembly and precise connections.

Another development is hybrid bonding, which can replace protruding connections with closely joined copper pads. Vardaman explained the electrical benefit of that approach:

Instead of a bump, we could do a pad-to-pad connection, which is almost no distance at all, and so that gives us better power performance,

The objective is to fit more connections into a small area while shortening the distance signals travel. It offers another way to improve data movement without depending entirely on a new transistor process.

Intel, assembly partners and equipment suppliers gain roles

Intel offers a different integration approach called Embedded Multi-die Interconnect Bridge, or EMIB. Rather than using a full interposer for the connections described in CoWoS, it places small silicon bridges where components need to communicate. Intel foundry services head Mark Gardner said this approach provides a cost advantage.

Intel's packaging customers include Amazon and Cisco, and Gardner said the company had served packaging customers since 2022. Reporting also describes plans for Intel to package custom chips for SpaceX, xAI and Tesla at Elon Musk's proposed Texas Terafab. Those plans should be distinguished from operating production capacity or completed deliveries.

TSMC, meanwhile, is expanding internal packaging work while also relying on outsourced semiconductor assembly and test companies, known as OSATs. Wei confirmed that tight capacity required cooperation with these partners. Some packaging steps have reportedly gone to ASE and Amkor, and ASE expects its advanced packaging sales to double in 2026.

Equipment suppliers are exposed to the same investment cycle. Applied Materials chief executive Gary Dickerson said in an August statement that packaging revenue was expected to grow more than 70% that year. The account does not identify the calendar year, so the figure should not be presented as a confirmed 2026 forecast.

These developments show that increased internal work at TSMC does not necessarily exclude specialist assembly companies. When demand exceeds capacity, the foundry, its partners and equipment vendors can all gain business from the same expansion.

The production dates that matter next

TSMC's official financial results give context to the investment push. Revenue reached $122.42 billion in 2025, up 35.9% in US dollar terms. Advanced processes of 7 nanometers and below accounted for 74% of wafer revenue, compared with 69% in 2024, a rise of five percentage points. These are company and wafer business figures, not a separate measure of packaging revenue.

The annual report says 2 nanometer technology entered high volume manufacturing in the fourth quarter of 2025. TSMC expects N2P and A16 production in the second half of 2026, confirming that transistor development continues alongside packaging expansion. The announced schedule now includes:

• April 16, 2026: TSMC confirmed tight advanced packaging capacity and capital spending toward the top of its $52 billion to $56 billion range.
• May 14, 2026: Executives announced 2026 mass production of 5.5-reticle-size CoWoS and outlined larger future platforms.
• Second half of 2026: N2P and A16 volume production is scheduled.
• 2027: New 3 nanometer production is scheduled in Tainan during the first half and Arizona during the second half.
• 2028: Japan's second fab and the 14-reticle CoWoS platform supporting 20 HBM components are scheduled for production.
• 2029: A CoWoS version supporting 24 HBM components is planned.

What is still missing is a completion date for Arizona's packaging facilities and a firm commercial production date for CoPoS. The larger CoWoS targets also do not establish which customers will receive capacity or how much will be available. TSMC's challenge is to turn rapid expansion into sufficient output at each required stage, while keeping increasingly large assemblies reliable.

Key Points

• TSMC says advanced packaging capacity remains tight despite rapid expansion.
• Its 5.5-reticle-size CoWoS platform is scheduled for mass production in 2026, with reported yield above 98%.
• Larger CoWoS platforms aim to support 20 HBM components in 2028 and 24 in 2029.
• Arizona wafer production still depends on packaging in Taiwan; completion dates for two planned US packaging facilities are undisclosed.
• Nvidia relies on CoWoS, while AMD's MI300 combines SoIC vertical integration with CoWoS.
• TSMC's 2026 capital spending is expected near the top of a $52 billion to $56 billion range covering multiple manufacturing investments.
• Intel, ASE, Amkor and equipment suppliers have growing roles as packaging becomes a constraint on AI hardware supply.