Samsung to Use TSMC 3nm Base Dies for Nvidia NVHBM as AI Memory Design Shifts

A shared manufacturing recipe for three memory suppliers

Nvidia has asked Samsung Electronics, SK hynix and Micron to use TSMC's 3nm manufacturing process for the base dies in its next generation of custom high bandwidth memory, according to industry accounts published on October 18, 2026. Samsung's Device Solutions division reportedly accepted the request after an internal review, bringing its Taiwanese foundry rival into a part of memory manufacturing Samsung has traditionally handled itself.

The product, called NVHBM, is based on HBM4E, the seventh generation of high bandwidth memory. Nvidia also wants suppliers to use the sixth generation of DRAM manufacturing technology for the memory dies, described as 1c. Its aim is to make memory from different suppliers behave more consistently and reduce the engineering work needed to approve each supplier's products.

Samsung's decision would extend an existing relationship with TSMC from packaging compatibility into HBM manufacturing. The companies worked together four years earlier to ensure Samsung memory could connect to graphics processors through TSMC's packaging technology. Producing an essential chip inside the memory stack takes that cooperation further.

Nvidia's proposal also changes what the base die does. NVHBM moves the memory controller, circuitry that directs the flow of data, from the main processor into the bottom of the memory stack. That makes the base die a more important part of the computing system, rather than simply a connection between memory and processor.

For Samsung, accepting that architecture means separating two decisions it previously kept together: who makes the memory that stores information, and who manufactures the logic chip that manages its connection to the processor. Samsung would continue supplying the memory while TSMC manufactures the specified base die.

What changes inside the memory stack?

HBM places several memory dies on top of one another beside a powerful processor. The stacked design lets large amounts of data travel over short distances, helping AI accelerators keep their computing units supplied with information. A die is an individual piece of silicon containing electronic circuits.

The core dies store data. The base die sits underneath them and handles connections and logic functions. In a conventional arrangement, the memory controller remains on the main accelerator die. NVHBM relocates that controller into the base die, freeing space on the processor for other circuitry.

Nvidia also uses a custom physical interface, known as a PHY, to connect the chips. The PHY is the circuitry that sends and receives electrical signals. Technical descriptions of NVHBM say it replaces the broad, parallel interface associated with standard HBM with a narrower, proprietary serialized connection, which sends data through fewer connections at higher speed.

The scale of the conventional interface helps explain the attraction. HBM4 has 32 channels, each 64 bits wide, making a total width of 2,048 bits. Managing those connections requires substantial circuitry and complex wiring between chips. NVHBM is intended to reduce that burden and simplify routing on the interposer, the connecting layer beneath the chips.

Nvidia is offering NVHBM as a building block for custom silicon partners through NVLink Fusion. Standard HBM remains a separate product category. Partners choosing NVHBM would use Nvidia's specified controller and connection design as part of their own accelerator systems.

Why Nvidia wants the same process across suppliers

Nvidia's proposed manufacturing recipe combines TSMC's 3nm logic process with advanced DRAM processes for the memory layers. Logic and DRAM perform different jobs and use different manufacturing methods. The 3nm label identifies a generation of logic manufacturing, while 1c identifies a generation of DRAM technology.

Samsung, SK hynix and Micron each have their own designs and production methods. Those differences can require additional testing when an accelerator developer wants to buy memory from more than one company. A common base die process gives developers a more consistent starting point.

Validation means checking that the processor, memory and package work together at the intended speed, power level and reliability. Repeating that work for different implementations takes engineering time. Nvidia's proposal seeks to reduce the amount of separate integration work needed when changing memory suppliers.

Micron calls its upcoming DRAM generation 1-gamma, which is broadly comparable to the 1c generation used in the terminology of Samsung and SK hynix. A unified target therefore brings together manufacturing generations with different company names, rather than making every supplier's memory process identical.

TSMC would become a common manufacturing partner beneath competing memory products. That arrangement could simplify Nvidia's implementation across suppliers while concentrating an important production step at one foundry. Samsung's examination of a backup manufacturing route reflects the practical importance of securing enough base dies.

Samsung keeps its own factories in the picture

Samsung plans to retain its integrated manufacturing model for standard HBM. Its HBM4 and HBM4E products use Samsung's own 4nm process for the base die and its 1c process for the core dies. The memory layers are manufactured at its Hwaseong and Pyeongtaek campuses in South Korea.

Samsung began mass production of HBM4 earlier in 2026, while HBM4E was undergoing qualification for mass production at the time of the October account. Qualification is the testing stage used to establish whether a product is ready to be manufactured consistently at the required standard.

Custom HBM for other customers, including AMD, is also expected to retain Samsung's integrated approach. The NVHBM decision is therefore specific to Nvidia's requirements, rather than a companywide move away from making base dies internally.

Samsung's Memory Business is expected to lead design and optimization support for base dies manufactured by TSMC. That would change the division of responsibilities inside Samsung, where System LSI and the Foundry business have traditionally contributed to internally sourced base dies.

Samsung is also assessing whether its own foundry could manufacture NVHBM base dies if demand exceeds TSMC's capacity. The proposed backup would preserve another production option, although the reported Nvidia specification currently centers on TSMC's 3nm process.

Micron and SK hynix take different routes

Micron's shift extends beyond Nvidia's custom product. The company says both NVHBM, developed with Nvidia, and its standard HBM4E will use base dies manufactured by an external foundry. TSMC is expected to handle that manufacturing.

For HBM4, Micron pairs memory dies made with its 1-beta process with a base die manufactured internally. HBM4E moves the memory layers to 1-gamma and moves base die production outside Micron's factories. Micron is therefore changing both major parts of the stack, using a newer memory process while adopting an external logic manufacturing partner.

Micron Chief Operating Officer Manish Bhatia expects NVHBM to achieve higher average selling prices and stronger margins. His reasoning is that HBM already sells at a premium, while the additional work and functions involved in customization create more value. Outsourcing the base die can therefore sit alongside an expectation of greater profitability.

SK hynix already uses TSMC's 12nm logic process for HBM4 base dies. Industry accounts indicate that TSMC's 3nm process is being prioritized for HBM4E and future custom HBM. The move would bring more advanced logic manufacturing to a component taking on additional responsibilities.

SK hynix has also shown a custom HBM concept based on its Stream DQ technology at Nvidia's GTC event earlier in the year. The concept focuses on managing and feeding data continuously to processors. Across all three suppliers, the common direction is to make the base die a more active participant in moving data.

What Nvidia's performance figures mean

Nvidia says NVHBM can provide up to 30% more bandwidth per stack than standard HBM4E and use 15% less HBM power. Bandwidth measures how much data can move in a given time. More bandwidth can help an AI processor that is waiting for information from memory.

Using a simple comparison, if a standard HBM4E stack delivers 100 units of data in a given period, Nvidia's maximum claimed improvement would raise that to 130 units. If the comparison memory uses 100 units of power, the claimed reduction would bring HBM consumption to 85 units. These examples translate the percentages, rather than describe particular shipping products.

Nvidia also describes freeing up to 25% of the XPU compute die's area. XPU is a broad term for a computing processor, including custom AI accelerators. Moving memory circuitry away gives designers room to allocate more of that silicon to computing functions.

Another account of Nvidia's presentation gives a figure of up to 30% more compute on the primary die. That measures potential computing resources, while the 25% figure describes silicon area released by the architectural change. Designers still have to decide how to use the recovered space.

The custom PHY is described as reducing the area occupied by that interface by as much as 67%. A technical assessment derives that estimate from the reduced pin count. Nvidia's broader bandwidth, power and area comparisons use standard HBM4E as their reference, at a stage when that generation had yet to ship.

For an AI service, faster data movement can help generate responses more quickly when memory is the limiting factor. Lower memory power can give system designers more room within an electricity budget. The effect on a complete server depends on the processor, workload, networking and cooling as well as the memory.

Amazon connects memory to Nvidia's wider platform

Amazon's Annapurna Labs is the first announced NVHBM partner. The chip design business develops Trainium accelerators for Amazon Web Services, giving Nvidia a route to supply memory technology to a company that also builds its own AI processors.

Nafea Bshara, vice president at Annapurna Labs, described the purpose of the partnership in comments accompanying the announcement:

We look forward to this technology collaboration to benefit future AWS infrastructure designs.

Annapurna's Trainium 4 is expected to support NVLink Fusion. Accounts of the NVHBM rollout place its introduction either with Trainium 4 or with a later generation; the exact chip generation and commercial availability date for Amazon's NVHBM implementation have not been settled publicly.

NVLink Fusion gives partners access to technologies including NVLink Chiplet, NVLink-C2C, NVLink Switch, and MGX systems and racks. These provide connections and system designs for bringing custom processors into Nvidia's computing infrastructure. NVHBM adds the memory subsystem to that collection.

MediaTek reportedly adopted NVLink Fusion five days after the NVHBM announcement and planned to offer it to its own XPU customers. That gives Nvidia another route into custom accelerator projects, a market where Broadcom and Marvell also compete. Marvell had described a comparable approach to relocating memory control in December 2024, making customer adoption and system integration important parts of the competition.

How the shift developed

NVHBM's development brings together changes in architecture, supplier relationships and customer adoption. The sequence helps explain why Samsung's October decision matters: Nvidia first presented the common design, and memory manufacturers then had to decide how to build it.

• December 2024: Marvell specified a comparable concept involving a different placement of memory control functions.
• Earlier in 2026: Samsung began mass production of HBM4, while SK hynix presented its Stream DQ custom HBM concept at GTC.
• August 26, 2026: Nvidia announced NVHBM as an addition to NVLink Fusion, naming Annapurna Labs as its first partner.
• Five days later: MediaTek reportedly adopted NVLink Fusion and planned to make it available to its XPU customers.
• October 18, 2026: Industry accounts described Nvidia's request for TSMC 3nm base dies and Samsung's acceptance following an internal review.

Samsung's decision brings the manufacturing plan closer to Nvidia's goal of a consistent implementation across memory suppliers. At the same time, Samsung's continued investment in its own base dies preserves a different route for standard HBM and custom products supplied to other customers.

Key Points

• Nvidia reportedly wants Samsung, SK hynix and Micron to use TSMC's 3nm process for NVHBM base dies.
• NVHBM moves the memory controller from the main processor into the HBM stack's base die.
• Samsung accepted the request but plans to retain internal manufacturing for standard HBM and other custom products.
• Micron plans external base die production for both NVHBM and standard HBM4E; SK hynix already works with TSMC on HBM4.
• Nvidia claims up to 30% more bandwidth and 15% lower HBM power consumption compared with standard HBM4E.
• Amazon's Annapurna Labs is the first announced partner, while Samsung is assessing its own foundry as a possible production backup.