Samsung Expands AI Memory Strategy With HBM5, AMD Memory Pooling and Faster Storage

Samsung puts memory capacity alongside processing speed

Samsung Electronics is extending its AI infrastructure strategy beyond high bandwidth memory, pairing HBM5 and customized memory with an AMD collaboration on shared server memory and storage technologies that move some data processing into SSDs. The company presented the approach at the OCP Global Summit 2026, scheduled for October 12 to 15 at the San Jose McEnery Convention Center in California.

The most concrete performance claims concern technologies elsewhere in the memory hierarchy. Samsung reports up to 38% less time before an AI model produces its first token through elastic CXL memory allocation, up to three times the inference performance with LPDDR5X processing in memory, and sequential SSD reads reaching 28.4 GB/s. These are results from particular evaluations or demonstrations, not guarantees for every AI installation.

Samsung's official summit page organizes its strategy around speed, memory expansion and persistence. Its featured products include HBM4E, LPDDR5X-PIM, the CMM-D MD310 memory module, SOCAMM2 server memory, and the PM1763 and BM1773 SSDs.

Hojun Shim, identified by Samsung as corporate vice president and head of the Memory Business Application Engineering Team, was scheduled to present the three priorities in an executive session on October 12. Reports describe the presentation as the launch of a broader effort to optimize processors, memory and storage together, rather than improve each component separately.

The distinction matters during inference, when a trained model generates answers. A fast accelerator can still spend time waiting for data, run short of memory as conversations grow, or encounter delays retrieving information from storage. Samsung is proposing different technologies for each of those constraints.

HBM5 headlines a wider speed strategy

Reports of the exhibition identify HBM5, described as eighth generation high bandwidth memory, customized HBM and zHBM among Samsung's speed initiatives. High bandwidth memory supplies large amounts of data to an accelerator through many parallel connections. Customized versions aim to match individual customers' system requirements.

The official product list names HBM4E rather than HBM5. Other accounts describe HBM4E and HBM5 concept mockups at the exhibition. That difference is important: an exhibit or concept presentation does not establish that a product is shipping, and Samsung's summit page does not give an HBM5 commercial release date or detailed performance specifications.

The strongest numerical evidence for processing speed comes from LPDDR5X-PIM. Processing in memory places some computation within the memory device, reducing repeated transfers between memory and a separate processor. Samsung says its design integrates processing units into each memory bank.

In an evaluation using Llama 3.1 8B on the Samsung Edge AI Accelerator, Samsung reports up to eight times the effective bandwidth of conventional LPDDR5X, up to three times the tokens generated per second, and runtime shorter by a factor of up to 2.2. These figures concern that accelerator and model, not HBM5 or the AMD memory demonstration.

SOCAMM2, also featured, is an LPDDR based server memory module. Together, the exhibits show that Samsung's speed strategy includes both accelerator memory and lower power memory technologies, although the summit page does not provide comparable benchmark results for every product.

AMD collaboration targets flexible memory capacity

Samsung and AMD demonstrated CXL memory expansion using Samsung's CMM-D technology. CXL, short for Compute Express Link, connects processors and other devices with additional memory, allowing systems to expand capacity beyond their directly installed memory.

CMM-D is a CXL based DRAM memory module. In a pooled configuration, multiple systems can draw capacity from connected memory resources instead of leaving that capacity assigned permanently to individual servers. Samsung says its AMD collaboration validated CXL as a way to scale memory capacity and bandwidth while reducing periods when CPU cores wait for data.

The problem becomes more pressing as AI agents run multiple models or tasks. Samsung's official description says agent workloads can sharply increase CPU use while memory capacity fails to keep pace with the number of processor cores.

A separate CMM-D pooling demonstration used elastic allocation across multiple large language model instances on a GPU server. Samsung reports up to 38% lower time to first token, or TTFT, and up to 3.3 times higher goodput than static allocation. TTFT measures the wait before a response starts; goodput measures useful work delivered under the evaluation's criteria.

Those results should not be treated as numerical results from the AMD demonstration itself. The official page describes the AMD validation and the elastic allocation benchmark separately. It also does not provide enough detail to establish how the gains would change with different models, server configurations or service targets.

KV cache connects memory expansion with storage

A central link between Samsung's memory and storage plans is the key value cache, usually called KV cache. It holds intermediate information generated as a language model processes text, allowing the model to reuse work instead of recalculating it for every new token.

Long conversations, larger contexts and multiple concurrent users can make these caches consume substantial memory. Samsung proposes a hierarchy in which CXL memory expands available capacity and SSDs hold cache data that does not need to remain in the fastest memory tier.

The official summit page describes a production deployment at Samsung Semiconductor's US campus serving an internal AI coding agent and other applications. Samsung says adding an L3.5 composable memory tier through its AI Memory Node solution delivered five to seven times the KV cache utilization.

L3.5 is the label used for that additional tier, not a claim that all servers share an identical cache architecture. The deployment involved Samsung's Memory Solutions Lab, its DSA AI Platform Integrations team and SGLang. The utilization result is distinct from both the elastic allocation benchmark and the LPDDR5X-PIM performance figures.

The summit schedule also included an October 13 session on combining CXL pooling with SSD storage for KV cache offloading, presented by system architect Jinin So and principal engineer Youngha Choi. That combination makes the strategy more than a capacity upgrade: it requires software to place and retrieve data across memory and storage without introducing excessive delays.

SSDs take on capacity, cooling and data placement

Samsung's persistence strategy centers on enterprise SSDs and high capacity NAND flash. Persistence means retaining data beyond the temporary working state of a computation, allowing AI systems to retrieve datasets, model files and saved cache information when needed.

The PM1763 is presented as a PCIe Gen6 enterprise SSD with sequential read speeds of up to 28.4 GB/s and power efficiency up to 1.8 times that of its predecessor. Samsung's liquid cooling demonstration places the E1.S version in direct contact with a cold plate to remove heat. The official page does not give a complete set of testing conditions for the performance comparison.

The BM1773 is listed as an E3.S SSD with 256TB of QLC storage. QLC, or quad level cell, stores four bits in each flash cell, supporting high capacity. Reports also describe Samsung's continuing development of high capacity QLC flash and flexible data placement technology.

Samsung demonstrated KV cache optimizations integrated into LMCache. Flexible Data Placement, or FDP, helps organize where data is written to reduce write amplification, the extra internal writing an SSD performs beyond the data submitted by the host.

The demonstration also uses a larger NVMe Maximum Data Transfer Size to reduce host CPU work. Samsung describes these techniques as relevant both to cache storage within a single node and to cache resources shared across a group of servers. It provides no numerical improvement for these particular optimizations on the event page.

Moving computation closer to stored data

Samsung's vector database demonstration offers another way to reduce data movement. Vector databases store numerical representations of information and compare them to find similar items, a common step when an AI application retrieves documents relevant to a request.

The NCVS proof of concept moves vector distance calculations into SSDs. Instead of sending a 4KB vector to the host for comparison, the device returns a four byte distance result. Samsung reports host traffic up to 22 times lower than the conventional host processing path, with search throughput increasing as more SSDs are added.

The four byte and 4KB figures describe the size of individual results and vectors; they do not mean the complete application cuts traffic by the same ratio. The reported reduction of up to 22 times is the broader measured comparison. Samsung identifies NCVS as a proof of concept, not a generally available product.

Its AiSIO demonstration addresses storage input and output through a common software interface for GPU initiated, peer to peer and conventional CPU initiated operations. Samsung reports 100 million input/output operations per second and up to ten times faster loading of language models from a cold start, using OpenDS.

These measures describe different jobs. Sequential read speed concerns sustained data transfer, input/output operations per second count storage requests, and cold start loading measures how quickly a model becomes ready. None is a direct substitute for a benchmark showing how many user requests a complete AI service can handle.

Customer testing and foundry exhibits widen the pitch

Samsung MAX Lab is intended to involve customers earlier in development. Customers can test technologies such as PIM, CMM-D and next generation SSDs before commercialization under realistic AI workloads, then feed system requirements into product design.

This approach addresses a practical issue running through the summit demonstrations: a faster component delivers value only if the software and surrounding hardware can use it. Samsung's Global Open-ecoSystem Team participates in open source development and industry standardization, while the event agenda includes sessions on software frameworks, storage command handling and memory management.

Samsung also demonstrated composable storage with live migration and virtual SSD management over standard NVMe. Its official description presents this as a route to storage shared among multiple tenants with enforceable quality of service, meaning controls over the service each workload receives.

The exhibition extended beyond memory. Reports describe Groq language processing unit wafers manufactured on Samsung Foundry's 4nm process, a Groq 3 LPX system described in several accounts as an Nvidia system, and wafers using Samsung's 2nm gate all around process. These exhibits present manufacturing capabilities alongside memory and storage, but do not establish new production contracts or shipment volumes.

A partnership developed across several months

The AMD demonstration follows earlier cooperation rather than standing alone. Reports describe a March memorandum of understanding covering next generation AI memory and computing technologies, followed by discussions during AMD chief executive Lisa Su's October 7 visit to South Korea.

The sequence of reported developments and scheduled summit sessions is:

• March 2026: Samsung and AMD signed their cooperation memorandum; Samsung also presented technology at Nvidia GTC.
• June and August 2026: Samsung presented at COMPUTEX and the Future of Memory and Storage conference, respectively.
• October 7, 2026: Lisa Su visited South Korea and met Samsung DS Division Vice Chairman Jeon Young-hyun to discuss memory and computing cooperation; reports also describe foundry discussions.
• October 12, 2026: The summit opened, with Shim's executive presentation scheduled that day.
• October 13 to 15, 2026: Samsung's program included KV cache tiering, storage optimization and shared CXL memory architecture sessions.

Samsung participated as a Diamond Sponsor. Reports differ on whether to date the strategy announcement to October 12 local time or the company's October 13 statement. Those dates can describe different stages of the same event. One account places the summit in San Francisco, while Samsung's official schedule identifies the San Jose convention center.

Market scale does not settle commercial readiness

Reported industry research puts Samsung first in the second quarter of 2026 with 39% of global DRAM revenue and 29.3% of the NAND flash market. Counterpoint Research is identified as the source of the DRAM figure and TrendForce of the NAND figure. These are market share measures, not shares of the emerging CXL or processing in memory markets.

Omdia is cited as forecasting the industry's largest DRAM and NAND wafer production for Samsung during the year. A separate estimate puts its annual DRAM capacity at approximately 8.175 million wafers equivalent to 300mm wafers. Capacity is not the same as actual output, and neither figure establishes how much production is allocated to the technologies shown at OCP.

One report also gives unusually large preliminary third quarter figures dated October 8: revenue of 195 trillion won and operating profit of 107.4 trillion won, with profit rising 782.5% from a year earlier. These figures are not substantiated by an official financial release here and should not be treated as established evidence of earnings from the summit technologies.

Competition is also moving beyond HBM. Reports describe SK hynix's Memory-Centric AI Rack System, or MARS, as a CXL memory pool shared across a rack. That parallels Samsung's effort to make spare memory accessible across systems, although no comparable benchmarks establish which approach performs better.

Samsung's stated ambition is to strengthen HBM, server DDR5 and enterprise SSD competitiveness. The unresolved commercial details include HBM5 availability, pricing, broader customer adoption and independent confirmation of the performance claims. The summit program supplies demonstration and discussion dates, not firm release deadlines for every technology.

Key Points

• Samsung's OCP 2026 strategy combines faster memory, CXL capacity expansion and persistent SSD storage.
• The AMD collaboration uses CMM-D memory technology to address growing AI memory demands.
• A separate elastic pooling demonstration reports up to 38% lower time to first token and 3.3 times higher goodput.
• LPDDR5X-PIM evaluation results include up to three times the inference performance on Samsung's Edge AI Accelerator.
• PM1763 storage, KV cache optimization and computation within SSDs target different data movement constraints.
• HBM5 shipment dates and broad commercial availability are not established by the summit disclosures.