CXMT Targets 2026 Launch of 4F2 Server Memory as Samsung Eyes 2028 Production

A smaller memory cell and an ambitious deadline

ChangXin Memory Technologies (CXMT), China's largest memory chipmaker, plans to introduce DDR5 registered server memory using a 4F2 DRAM architecture by the end of 2026. President Cao Kanyu outlined the plan on October 10 at the Fourth Integrated Circuit and Chiplet Conference in Shanghai, putting a specific product and deadline behind the company's bid to compete with Samsung Electronics, SK hynix and Micron.

The proposed architecture reduces the area occupied by an individual memory cell from the mainstream 6F2 design to 4F2. At the same minimum feature size, that represents a theoretical reduction of one third in cell area. It could allow more memory to fit on a chip, although the gain in a finished product will depend on circuitry, manufacturing results and other design requirements.

CXMT's deadline precedes Samsung's reported 2028 target for mass production by roughly two years. That is not yet evidence of a two year manufacturing lead. Introducing a product and producing it reliably in large quantities are different milestones, and CXMT has not disclosed detailed specifications, an exact release date or production yields for the planned server memory.

The announcement matters because it targets enterprise servers rather than the consumer devices where Chinese DRAM suppliers have already established a presence. Server customers need dependable operation over long periods, making commercial acceptance a separate test from demonstrating a smaller cell.

What Cao announced in Shanghai

Cao Kanyu, whose name also appears as Chao Kanyu in English reports, said server memory would be the first product application for CXMT's new architecture. He described the intended release at the Shanghai conference:

We will launch next-generation DDR5 RDIMM server memory incorporating a 4F2 DRAM structure by the end of the year.

RDIMM stands for registered dual inline memory module. These modules use a register to buffer command and address signals, helping servers support demanding memory configurations. DDR5 identifies the memory generation; 4F2 describes the underlying cell layout. The announcement therefore concerns a new way of building the chips inside a familiar category of server memory, rather than a replacement for the DDR5 standard.

CXMT said it redesigned key manufacturing steps and developed its own vertical surrounding gate transistor, or VSG. Those claims suggest work extending beyond a proposed cell layout. They do not establish how many usable chips the process produces, how quickly production can expand or whether server customers have completed qualification.

Reports differ in how strongly they describe the deadline. Some present it as a plan to begin mass production around the end of the year, while Cao's quoted statement promises a product launch. Without disclosed manufacturing volumes, the narrower launch commitment is the firmer basis for comparing CXMT with its competitors.

What 4F2 changes inside a DRAM chip

DRAM stores information in cells that must be refreshed regularly to retain their data. In the notation used for cell size, F represents the minimum feature size, commonly described as the minimum line width. A 4F2 cell occupies an area equivalent to 2F multiplied by 2F, compared with six square units of F for a 6F2 cell.

The arithmetic gives a useful measure of the ambition. Moving from six units of area to four cuts the cell footprint by about 33%. If only cell area mattered, the same space could contain 50% more cells, because six divided by four equals 1.5. Neither figure should be read as a promised improvement in the capacity or speed of CXMT's finished modules.

Real chips also need peripheral circuits, connections and space determined by manufacturing constraints. Memory speed, power consumption and reliability depend on more than the number of cells that fit into a given area. CXMT has not published measurements that would allow those product characteristics to be compared with current server DRAM.

The proposed VSG transistor places the channel vertically, with the gate surrounding it. The gate controls current through the transistor. CXMT says this arrangement helps reduce unwanted current leakage and increases memory density, with potential benefits for power efficiency.

CXMT is also exploring hybrid bonding to optimize memory cells and peripheral logic separately. Hybrid bonding joins semiconductor structures through very fine electrical connections. The stated goal is to give the storage array and its supporting circuitry greater design flexibility, although reports do not establish whether that approach will be used in the initial DDR5 RDIMM release.

Samsung and SK hynix have their own schedules

Samsung Electronics and SK hynix are researching 4F2 DRAM, but neither has announced a firm mass production commitment in the accounts of CXMT's announcement. SK hynix disclosed a related technology roadmap in 2025. Samsung reportedly aims to complete development of its 10a DRAM using 4F2 in 2026, conduct quality testing in 2027 and begin mass production in 2028.

The Samsung schedule is a reported development target, not a confirmed guarantee. It nevertheless explains the attention paid to CXMT's proposed 2026 release: the Chinese company is seeking to introduce a commercial product before the production date currently associated with its larger rival.

Tian Feng, a researcher at Shanghai Jiao Tong University, said the three major memory manufacturers have roadmaps for 4F2 or similar 3D DRAM technologies but have not reached large scale commercialization. His assessment supports the view that this is an emerging competition, rather than a market in which one manufacturer has already proved a decisive lead.

The reported milestones span several years:

• 2016: CXMT says it began researching 4F2 when the company was founded.
• 2025: SK hynix disclosed a roadmap related to 4F2 technology.
• August 2026: CXMT says it began mass production of LPDDR6 mobile memory.
• September 2026: CXMT says its fifth generation DRAM manufacturing platform entered mass production.
• October 10, 2026: Cao presented the server memory plan in Shanghai.
• End of 2026: CXMT targets the introduction of DDR5 RDIMMs using 4F2.
• 2027 and 2028: Samsung reportedly plans quality testing followed by mass production.

Why production yield may decide the contest

The central manufacturing issue is yield, the proportion of chips produced on a wafer that meet the required specifications. A smaller cell can be attractive in principle while remaining expensive to manufacture if too many chips fail testing. Changing transistor geometry and production steps means the process must be brought to a commercially useful yield.

That is particularly important during a memory shortage. Manufacturers introducing a new process risk losing usable output while they resolve production problems, even if the technology ultimately improves density or performance. Established suppliers therefore have a reason to weigh the timing of a transition against demand for their existing products.

Kim Jin-guk, former chief technology officer at SK hynix, described production capacity as the immediate commercial priority:

With the current memory shortage expected to last, the market is shifting to one where production capacity matters more than technological prowess,

Kim also warned about the cost of introducing a new process:

Production losses during the introduction of new technologies are bound to be significant.

His comments explain why an earlier announcement does not necessarily mean a stronger competitive position. A company making large quantities of dependable memory can serve customers more effectively than a rival with a denser design that is still difficult to manufacture.

CXMT's reported September start of production on its G5 platform shows activity on another manufacturing milestone. It does not, by itself, prove that the announced 4F2 server product has reached equivalent readiness. The company has not disclosed the relationship between those production claims in enough detail to draw that conclusion.

Server customers are a different test

Samsung, SK hynix and Micron have held leading positions in server DRAM, while CXMT has focused more heavily on consumer electronics. CXMT says the contribution from its server business increased in the first half of 2026, but the reports give no revenue figure or market share for that business.

That leaves an important distinction between entering the server market and winning substantial demand there. Customers need memory that works reliably with their systems under sustained workloads. Product qualification, dependable deliveries and consistent performance will matter alongside chip density.

The announcement also does not establish a breakthrough in high bandwidth memory, or HBM, which is widely used alongside advanced computing processors. DDR5 RDIMMs and HBM serve different memory roles. Progress in the proposed server product cannot be treated as proof that CXMT has closed its reported HBM technology gap.

Estimates of China's distance from South Korea in conventional DRAM differ. Some accounts put it at one to two years, while others describe a gap of two to three years. The accounts broadly place the HBM gap at at least three years. These are industry assessments, not measurements derived from disclosed, comparable product tests.

Patents and equipment shape the wider race

CXMT says it has published more than 300 patent families related to 4F2 and has researched the architecture since 2016. A patent family groups related applications protecting an invention across filings or jurisdictions. The count indicates a substantial body of claimed intellectual property, but it is not the same as 300 separately proven manufacturing advances.

Cao also claimed CXMT's related patent holdings exceed those of domestic and international competitors. No comparative patent dataset is given to verify that ranking. The more useful commercial tests will be whether the designs can be manufactured, whether the resulting products meet customer requirements and whether they can be supplied at scale.

Equipment access remains another constraint. CXMT cannot use ASML's extreme ultraviolet lithography equipment, known as EUV, according to the reports. EUV helps manufacturers pattern extremely small features, and its absence adds uncertainty to CXMT's route toward commercially useful yields.

Some industry commentary argues EUV will have less influence on future 3D DRAM production. That expectation concerns a later architecture and does not remove the manufacturing challenges facing the announced product. A vertical transistor in a 4F2 cell is also not automatically the same thing as stacking multiple layers of DRAM cells.

Other reported Chinese developments help explain the concern among Korean manufacturers. Huawei has promoted logic folding technology, while reports describe Samsung paying royalties for use of YMTC's Xtacking bonding technology. These involve different technologies and companies, so they cannot validate CXMT's server memory claims.

A reported patent licensing agreement announced by Huawei and Qualcomm on October 5 covers 5G, computing, artificial intelligence and networking. It illustrates the broader role of Chinese intellectual property in the industry, but it is not a DRAM agreement or evidence of 4F2 production readiness.

What remains unproven before the deadline

CXMT's financial expansion provides further context for its development push. Reports put its July share sale at about $8.6 billion, or roughly 66.61 billion yuan, and describe a 466% increase in its shares on the first trading day. Those figures show substantial financing and investor interest, not technical validation of the planned memory product.

The immediate stock reaction among established suppliers was modest: Micron fell about 1% in overnight trading and SK hynix declined 0.8% in local trading in the reported sessions. Wider semiconductor selling and concerns about artificial intelligence spending were also present, so the moves cannot be attributed solely to CXMT's announcement.

The next stated deadline is the end of 2026. Before a direct competitive comparison is possible, CXMT needs to disclose more than a release date: module specifications, production scale, customer qualification and evidence of reliable operation would help establish what the announcement means commercially.

For now, CXMT has set an earlier product target than Samsung's reported manufacturing schedule and described a concrete architectural approach. Whether that becomes an advantage in server memory depends on usable output and customer adoption, not the calendar alone.

Key Points

• CXMT plans to introduce DDR5 registered server memory using 4F2 DRAM by the end of 2026.
• A 4F2 cell is theoretically one third smaller than a 6F2 cell at the same minimum feature size.
• CXMT says its vertical surrounding gate transistor reduces leakage and supports greater density.
• Samsung reportedly targets 2028 mass production; SK hynix disclosed a related roadmap in 2025.
• CXMT has not disclosed detailed product specifications, production yields or an exact launch date.
• An earlier launch would not, on its own, establish a lead in large scale manufacturing or server customer adoption.