China's Analogue AI Chip Shows 12 Times Faster Processing, With Larger Gains Projected

Peking University moves analogue computing into practical AI tasks

Peking University researchers have demonstrated an analogue computing chip that trains recommendation systems 12 times faster than advanced digital processors while using just one two-hundredth of the energy. Published in Nature Communications during the week of January 28, 2026, the study tested workloads using datasets comparable in scale to those employed by Netflix and Yahoo.

The results take the technology beyond basic mathematical demonstrations into personalized recommendations and image processing. The chip uses resistive random-access memory, or RRAM, to perform calculations where information is stored, reducing the movement of data between separate memory and processing units.

Sun Zhong, the study's lead author and an assistant professor at Peking University, described the practical demonstrations as another advance for analogue computation:

This pushes the boundary of analogue computing one step further.

The latest results follow an announcement in October, when the team said it had addressed the precision problem that has long limited analogue machines. At that time, researchers projected processing rates as much as 1,000 times faster than leading digital processors such as Nvidia's H100 graphics processing unit, with 100 times better energy efficiency.

The practical recommendation results put the speed improvement at 12 times, while energy use fell to one two-hundredth of the digital comparison. The larger projection concerns particular matrix calculations, the mathematical operations at the heart of the chip's design. Its immediate role is as a specialist processor for those operations.

China's restrictions on access to advanced imported processors give the research added relevance. So does the rising electricity demand of AI infrastructure: some data centers already consume power on a scale comparable to small cities, and training a single large language model can consume megawatt-hours of electricity.

How electrical signals replace strings of binary instructions

Conventional digital computers represent information using zeros and ones. Analogue computers work with continuous physical quantities, such as electrical current. A light switch provides a simple comparison: digital operation resembles a switch that is either on or off, while analogue operation resembles a dimmer that can move through a range of settings.

The Peking University chip uses those changing electrical signals to calculate through the physical properties of its circuits. Instead of breaking every calculation into a long sequence of binary operations, it can process groups of numbers in parallel within memory arrays.

RRAM cells store information by changing the electrical resistance between electrodes. Resistance determines how readily current passes through a component. These cells function as memristors, components that retain a memory of earlier current flow through changes in their internal resistance.

The same physical location can therefore hold information and participate in a calculation. Conventional computers repeatedly transfer data between memory and processors across connections called bus lines. Those transfers consume energy and can limit how quickly a processor receives the information it needs.

Matrix operations are especially suited to this approach. A matrix is a grid of numbers, and calculations involving these grids underpin artificial intelligence, machine learning and wireless communications. Neural network training and signal processing for future 6G networks both depend on such work.

Digital processors break matrix calculations into many binary operations. The analogue chip performs the relevant mathematical work directly through its memory circuits, without converting each calculation into binary code. That architectural change offers a route to better performance as semiconductor components approach the atomic scale and further advances in fabrication become harder.

Two circuits tackle the precision problem

Analogue computing has historically struggled to deliver reliable precision. Interference and electrical noise can alter signals, creating errors that become troublesome in complex calculations. Digital systems use algorithms that proceed step by step to achieve exact results within their numerical format.

Sun described accuracy and the ability to handle larger problems as the central challenge facing the technology:

Precision has long been the central bottleneck of analogue computing. How to achieve both high precision and scalability in analogue computing, thereby leveraging its inherent advantages for modern computing tasks, has been a century old problem plaguing the global scientific community.

The Peking University design divides the work between two circuits. The first produces a rapid approximate answer. The second repeatedly refines that answer, combining the speed of analogue computation with accuracy comparable to digital calculation using floating point numbers represented with 32 bits.

The initial circuit produces results with an error of approximately 1 percent. After three refinement cycles through the second circuit, the error falls to a level comparable to standard digital processors. Sun said the method improves traditional analogue precision by five orders of magnitude, or roughly 100,000 times.

The researchers demonstrated the approach by solving matrix inversion problems involving grids of 16 by 16 real valued numbers, achieving fixed point precision represented with 24 bits. Matrix inversion is a mathematical operation used to work backward through a set of numerical relationships and solve related equations.

Fixed point and floating point are ways of representing numbers with a limited number of bits. Fixed point keeps the numerical scale in a set position; floating point allows it to move so that a wider range of values can be represented. Both descriptions help specify the accuracy achieved by the chip.

An old computing idea gains a modern implementation

Analogue computing predates digital technology by centuries. The Antikythera mechanism, a Greek astronomical calculator from about 2,000 years ago, used interlocking gears to predict celestial positions. Its calculations arose from the movement of physical parts rather than electronic binary instructions.

A Soviet water integrator built in 1936 used fluid moving through tubes to solve mathematical equations. Like the electrical signals in the new chip, the movement of water represented quantities involved in a calculation.

Noise and difficulties in scaling up analogue systems helped push these machines aside as digital computing matured. The new research returns to the idea of using physical behavior to calculate, but implements it with modern resistive memory and an architecture designed to correct errors.

The development has progressed from an accuracy claim to practical demonstrations:

• About 2,000 years ago, the Antikythera mechanism used gears for astronomical calculations.
• In 1936, the Soviet water integrator used flowing water to solve equations.
• In October, the Peking University team announced its approach to the precision problem and projected gains of up to 1,000 times in speed and 100 times in energy efficiency.
• During the week of January 28, 2026, the Nature Communications study demonstrated recommendation training, image processing and wireless signal applications.

The modern contribution is the combination of resistive memory, parallel computation and repeated refinement. Together, those elements allow a physical computing method associated with earlier machines to address numerical tasks used in contemporary AI.

Recommendations and images put the chip to work

Recommendation systems provided a practical test of the chip's capabilities. The researchers trained systems using datasets comparable in scale to those used by Netflix and Yahoo, demonstrating that the design could handle work beyond simple mathematical benchmarks.

Streaming services, social media platforms and online shops use recommendation algorithms to turn user activity into suggestions. Across these services, the algorithms process billions of interactions. Much of that work involves finding numerical relationships between users, items and earlier choices.

The reported 12 times speed improvement and energy use of one two-hundredth of the digital comparison make this an important application for the design. Recommendation training provides a setting in which its strengths in matrix operations can contribute to a recognizable computing task.

Image compression supplied another test. The system reconstructed visual data with quality nearly identical to computation at full digital precision while reducing storage requirements by half. Compression makes files smaller; reconstruction turns that smaller representation back into an image.

Smaller image files can reduce both storage needs and the amount of data sent over a network. Those demands matter in video streaming and medical imaging, among other uses. The researchers' demonstration paired reduced storage with image quality close to the full precision digital result.

The applications also clarify why accuracy matters. A fast mathematical answer has limited value if errors make recommendations or reconstructed images unusable. The dual circuit approach aims to preserve the efficiency of analogue calculation while delivering the precision these workloads require.

Wireless tests point toward 6G applications

The chip also detected signals in massive multiple-input multiple-output systems, a wireless technology that uses large groups of antennas. Processing signals from many antennas requires substantial mathematical work to separate and interpret communications.

In these tests, the device matched digital processor performance while using approximately 100 times less energy. That result gives telecommunications a distinct place among the possible applications, alongside recommendation training and image compression.

Future 6G base stations are expected to manage hundreds of antenna elements at once. They must process large amounts of signal data in real time to maintain connections with mobile devices. The combination places pressure on processing speed, electricity use and the time allowed to deliver an answer.

The computational demands described for these systems exceed the capabilities of current digital signal processors, particularly within the delay limits and power budgets of remote cellular towers. A processor that performs the required matrix work with less energy could help address those constraints.

Wireless infrastructure also illustrates why power savings can matter outside a large data center. Equipment may operate where cooling capacity or available electricity is limited. The communications demonstration offers a potential use for the chip in environments where efficiency directly affects what hardware can be deployed.

Why the energy savings matter for AI infrastructure

Large language model training can run for weeks across thousands of advanced graphics cards. Such work consumes megawatt-hours of electricity, while data centers worldwide collectively use more power than some developed nations.

The chip's recommendation benchmark combines two improvements: faster processing and less energy required for the task. Using one two-hundredth of the comparison's energy means a large reduction in the electricity spent on that computation. The wireless tests produced a different result, at approximately one-hundredth of the energy used by the digital comparison.

Those savings could reduce operating costs and the environmental impact of the workloads the chip can accelerate. Data centers are already consuming increasing shares of global electricity production, making the energy cost of AI development a growing concern.

Nvidia's H100, cited in the earlier performance projection, is among the graphics processors used to train large language models, including ChatGPT. The projected gain of up to 1,000 times in throughput applies to specific matrix operations. Sun cautioned that practical applications may achieve smaller gains than theoretical maximums.

The chip accelerates matrix computation, so the amount of benefit depends on how much of a task consists of that work. A training process dominated by suitable matrix calculations could gain substantially. A general computing job requiring many different operations would receive a more limited benefit.

This makes the choice of workload central to the technology's value. Its energy advantage is most useful when the calculations it performs efficiently account for a large part of the processing required.

China's chip restrictions and the manufacturing question

China faces export restrictions limiting access to advanced Nvidia GPUs and other powerful digital processors. The Peking University development offers a domestically developed alternative for particular calculations used in AI training and inference, the process of using a trained model to produce results.

The chip specializes in matrix work rather than the full range of operations performed by a general purpose graphics processor. Its potential place in AI hardware is therefore as an efficient option for a defined set of tasks.

James Millen, a researcher at King's College London, described digital computers as universal machines capable of calculating anything, while explaining that they do not necessarily calculate everything efficiently or quickly. Analogue machines tailored to particular tasks can achieve very high speed and efficiency for those applications.

Millen's explanation connects the research to the growing electricity requirements of AI. A specialized machine can use a different physical approach to perform selected calculations with less energy, while digital hardware retains the flexibility needed for other work.

The researchers fabricated the chips using commercial foundry capabilities and standard semiconductor manufacturing techniques. Production could therefore potentially expand through existing supply chains rather than requiring exotic materials, entirely new fabrication facilities or billions in investment in new infrastructure.

That manufacturing approach gives the project a practical basis beyond the laboratory. Commercial deployment still requires further engineering, including larger and more integrated devices. The next goals are to build fully integrated chips able to solve more complex problems at higher speeds.

Larger matrices and hybrid processors are the next challenge

Scalability remains a major challenge. Digital computers can divide a large problem into smaller pieces and process them in sequence. Analogue systems need physically larger circuits to solve larger matrices, making the expansion of their computing capacity an engineering problem.

The demonstrated 16 by 16 matrix calculations are far smaller than the problems involving grids of a million by a million variables described for modern large language models. Building devices capable of handling those demands would require substantial advances.

Hybrid architectures offer a possible direction. A future graphics processor could contain analogue circuits for selected parts of AI training, including linear algebra operations and second order optimization methods, while retaining digital cores for general computing.

Second order optimization uses information about how a model's error changes to guide training adjustments. It is one example of the mathematical work that could be assigned to specialized analogue hardware. Integrating such circuits into commercial graphics processors remains years away, and no product launch date was given.

Edge computing is another potential application. Autonomous vehicles, industrial robots and augmented reality headsets need substantial processing power while operating within battery and heat limits. Current solutions can depend on sending data to cloud servers, introducing delays and reliance on a network connection.

Smaller analogue chips could potentially carry out complex AI inference directly on such devices with less energy. That could extend battery life and allow more independent operation, particularly where power consumption is the main constraint.

The team's next steps are larger, fully integrated chips that handle more complex problems faster. Success could support more efficient AI training, help future 6G communications and reduce the electricity required for suitable data center tasks. The immediate achievement is a working demonstration that combines analogue efficiency with enough precision for several practical applications.

The Bottom Line

• Peking University researchers demonstrated recommendation training 12 times faster than advanced digital processors while using one two-hundredth of the energy.
• The earlier projection of up to 1,000 times greater speed and 100 times better energy efficiency concerns specific matrix operations.
• Two circuits produce and refine approximate answers, improving traditional analogue precision by roughly 100,000 times.
• The team demonstrated matrix inversion for grids of 16 by 16 numbers with fixed point precision represented with 24 bits.
• Image reconstruction achieved quality close to full precision digital computing while halving storage requirements.
• Wireless signal tests matched digital performance using approximately 100 times less energy.
• Commercial semiconductor processes were used to fabricate the chips, but larger devices and integration into practical systems require further development.
• The technology offers a specialized option for AI and communications as China faces restrictions on advanced imported processors and AI electricity demand grows.