Huawei Kunpeng 930 Leak Points to 5nm Compute Dies, With TSMC or SMIC Origin Unresolved

A server processor at the center of a manufacturing mystery

Huawei's Kunpeng 930 has emerged in leaks and teardown reports with a striking combination: 120 ARM-based TaiShan cores, four compute dies reportedly made on a 5nm process, and a separate, much larger die handling input and output. As of August 31, 2025, the central question is who manufactured its most advanced components, Taiwan's TSMC or China's SMIC.

The answer matters to more than the processor's specifications. US restrictions have severely limited Huawei's access to advanced manufacturing at TSMC since 2020. A chip made using previously produced TSMC components would tell a different supply story from one built with a newer process developed by SMIC, China's leading chip foundry.

Most of the technical teardown assessments described so far point toward TSMC's N5 process for the compute dies. Other explanations include components manufactured before restrictions took full effect, stockpiled wafers, or progress in SMIC's own manufacturing technology. The manufacturer, production timing and sourcing arrangements remain unresolved, while benchmark results are still awaited.

The Kunpeng 930 succeeds the Kunpeng 920, which debuted in 2019 using a 7nm manufacturing process. Its reported design combines advanced compute components with an input/output die made using a more mature process, possibly 14nm. That arrangement places the processor at the intersection of Huawei's server ambitions, China's drive for greater semiconductor independence and the practical limits imposed by access to manufacturing.

What the reported specifications reveal

The Kunpeng 930's reported specifications describe a processor intended for demanding server applications. Its 120 TaiShan cores are distributed across four compute dies, with 2MB of L2 cache per core and 91MB of shared L3 cache. Cache is memory close to the processing cores that keeps frequently needed information readily available.

The processor also reportedly supports 96 PCIe lanes and 16 channels of DDR5 memory. PCIe provides connections to other hardware, while memory channels give the processor routes for exchanging data with system memory. The original technical descriptions refer to PCIe 4.0/5.0 support, alongside compatibility with motherboards carrying two processor sockets.

The main reported specifications are:

• 120 ARM-based TaiShan cores across four compute dies.
• 2MB of L2 cache per core and 91MB of shared L3 cache.
• 96 PCIe lanes for connectivity.
• Support for 16-channel DDR5 memory.
• Compatibility with server motherboards using two processor sockets.
• A package measuring about 77.5mm by 58.0mm.

The input/output die is described as more than 80% larger than its predecessor. Its increased size reflects the demands of greater memory capacity for data transfers and expanded connectivity. The entire package brings these separate pieces together as one processor.

Huawei developed the TaiShan cores internally. Their use reflects the company's effort to control more of its processor architecture and tailor it to Chinese enterprise workloads, rather than relying entirely on designs shaped around other markets.

Why TSMC is the leading explanation

The manufacturing origin discussion, the server chip teardown and the N5 manufacturing assessment describe compute tiles made on a 5nm process, with strong indications pointing toward TSMC. Independent teardown assessments on YouTube and BiliBili also favor TSMC's N5 process for those components.

TSMC, based in Taiwan, is the world's leading manufacturer of advanced chips. Its possible involvement is especially sensitive because US sanctions have restricted Huawei's access to its most advanced manufacturing processes since 2020.

Some analysts suggest that the relevant components could have been manufactured before those restrictions took full effect. Another possibility is that Huawei stockpiled wafers, the material on which chips are manufactured, for later use. Both explanations would connect the processor to an earlier supply of advanced components.

The reported 5nm designation describes the manufacturing process used for the compute dies. It is a technology label, useful for identifying a generation of production, rather than a complete description of the finished processor's speed, power consumption or manufacturing history.

Where SMIC could fit into the package

SMIC appears in two parts of the manufacturing discussion. One is the possibility that it developed a process close to TSMC's 5nm technology. The other is the suggestion that it manufactured the Kunpeng 930's input/output die, while TSMC supplied the compute dies.

The proposed advanced SMIC process is known as N+3. It has been described as offering transistor density between TSMC's N6 and Samsung's 5nm processes. Transistor density describes how many of the tiny electronic switches used to process information can fit into a given area.

The descriptions of the input/output die are less consistent: it has been attributed to SMIC using either a 14nm process or N+3. The broader design explanation places this component on a more mature manufacturing process than the compute dies.

A combination of TSMC compute dies and an SMIC input/output die would give Huawei a processor assembled from components with different manufacturing origins. An explanation attributed to an unnamed industry analyst describes the reasoning behind that approach:

The hybrid approach allows Huawei to maximize performance where it matters most—compute and cache—while leveraging domestic manufacturing for less critical I/O functions.

Huawei's manufacturing options are therefore tied to both engineering choices and supply constraints. The compute components carry the most demanding processing work, while the separate input/output component supports the movement of data and connections to the rest of the server.

How separate dies work together

The Kunpeng 930 uses a chiplet design, meaning that several smaller pieces of silicon perform different jobs within the same processor package. Its four compute dies and separate input/output die divide work that could otherwise be concentrated on one larger piece of silicon.

The compute dies handle processing, cache and memory control. The input/output die manages connectivity and data routing. Dividing those responsibilities allows the designer to choose a manufacturing process suited to each component instead of requiring every part to use the same process.

Smaller dies can also be easier and cheaper to manufacture because defects affect less silicon at a time. A more mature manufacturing process can offer better yields, meaning a larger proportion of the components produced work as intended. These are among the reasons chiplets can help control manufacturing costs.

The design also offers a route to scaling the processor by adding compute chiplets, and therefore more cores and cache. Using components from different foundries can provide supply flexibility when sanctions or shortages limit access to a particular manufacturer.

AMD and Intel have adopted chiplet designs in their latest server processors as well. Huawei's reported arrangement follows that broader engineering approach, while also responding to its own restrictions on access to advanced production.

How it compares with AMD and Intel

The reported 120 cores and large cache capacity place the Kunpeng 930's specifications in the same broad discussion as AMD's EPYC processors and Intel's Xeon Scalable family. Its DDR5 support, PCIe connectivity and compatibility with two processor sockets make it relevant to a range of cloud and data center applications.

The manufacturing comparison is less favorable. The manufacturing restrictions assessment connects Huawei's reliance on older processes to US export controls that have blocked access to newer technologies. By August 2025, 5nm was described as a process generation about five years old, while leading competitors were moving toward 3nm and even 2nm technologies.

Server performance depends on more than a manufacturing label or core count. Memory bandwidth determines how quickly data can move between memory and the processor. Input/output efficiency affects communication with other hardware. Software support determines how effectively applications use the available processing resources.

Huawei's TaiShan cores also face competition from the mature x86 software ecosystem associated with AMD and Intel. Software and firmware optimization will be important for demanding server workloads, particularly where applications need to make efficient use of many cores.

China's domestic market gives the processor another source of relevance. Buyers placing greater weight on supply resilience and domestic technology may value a processor differently from customers focused mainly on the newest manufacturing process. The Kunpeng 930's commercial appeal will depend on that balance as well as its eventual measured performance.

The dates behind the supply challenge

Huawei's server development has unfolded alongside tightening US restrictions. The Kunpeng 920's launch and the first sanctions targeting Huawei both date to 2019, followed by severe restrictions on access to TSMC's advanced processes from 2020.

The main dates connect the processor's development to the wider technology dispute:

• 2019: Huawei introduced the Kunpeng 920 using a 7nm process. US sanctions began targeting Huawei's access to advanced chipmaking tools and foundries.
• 2020: Restrictions severely limited Huawei's access to TSMC's most advanced manufacturing processes.
• August 31, 2025: Kunpeng 930 leaks and teardown assessments pointed to a design combining reported 5nm compute dies with a separate input/output die.
• 2026: Huawei reportedly aimed to complete a design milestone known as tape-out for 3nm Gate-All-Around chips.

US controls aim to slow China's progress in critical technologies by limiting access to advanced tools and manufacturing services. Huawei's reported processor design shows how a company can continue developing server products while working within a more constrained supply chain.

For China, the project sits within a broader effort to develop domestic foundries, materials and technical talent. Investment in those areas is intended to reduce dependence on overseas suppliers for the infrastructure used in computing and communications.

Huawei's ambitions beyond the Kunpeng 930

Huawei is reportedly investing in technologies beyond the manufacturing processes discussed in the Kunpeng 930 teardown. Those efforts include 3nm Gate-All-Around technology, known as GAA, and carbon-based transistors.

The reported 3nm development plans include a goal of reaching tape-out by 2026. Tape-out is the stage at which a chip design is finalized for manufacturing. GAA describes a transistor structure in which the controlling gate surrounds the channel carrying current.

The proposed work would bring Huawei into competition with the advanced manufacturing ambitions of Samsung and TSMC. Carbon-based transistors represent another area of research mentioned alongside its efforts to develop future chip technologies.

A Huawei spokesperson described the company's objective in terms of domestic infrastructure and technological independence:

Our goal is to achieve technological independence and provide world-class solutions for China's digital infrastructure.

The Kunpeng 930 belongs to that wider ambition, but its immediate engineering demands are concrete. Components made using different processes must work together reliably, while firmware and software must coordinate processing, memory access and communication across the package.

What server buyers will need to assess

The Kunpeng 930's reported configuration gives Chinese server builders a potentially capable processor for enterprise and cloud systems. Its combination of many cores, substantial cache, broad memory connectivity and support for two processor sockets addresses several of the requirements of demanding computing workloads.

Integrating dies from different foundries can introduce compatibility and performance challenges. The processor package must connect its components effectively, and the supporting software must make good use of that design. Those tasks are central to turning an ambitious set of specifications into a dependable server platform.

For customers, manufacturing access and usable performance are closely connected. A processor that fits domestic supply priorities still needs to run applications efficiently, communicate with memory and attached hardware, and work within an established software environment.

Huawei's reported design therefore brings two developments together: a substantial change from the Kunpeng 920 and a manufacturing strategy shaped by restrictions. Its strongest immediate significance lies in that combination, while measured performance and a confirmed account of component production remain the next pieces needed to judge the finished product.

Key Points

• The Kunpeng 930 reportedly combines 120 TaiShan cores across four compute dies with a separate input/output die.
• Reported specifications include 91MB of shared L3 cache, 2MB of L2 cache per core, 96 PCIe lanes and 16-channel DDR5 support.
• Most cited teardown assessments favor TSMC's N5 process for the compute dies; pre-restriction production, stockpiled wafers and SMIC manufacturing remain part of the sourcing discussion.
• The input/output die has been attributed to SMIC, with descriptions citing 14nm or N+3 manufacturing.
• US restrictions have severely limited Huawei's access to advanced TSMC production since 2020.
• Benchmark results are awaited, and Huawei reportedly aims for a 3nm GAA tape-out in 2026.