Japan Materials Suppliers Expand as Chipmakers Prepare for 2 nm Production

Japanese suppliers prepare for a more demanding generation of chips

Japan's semiconductor materials companies are expanding production and upgrading technology as global chipmakers move toward mass production of 2 nanometer logic chips. Tokyo Ohka Kogyo plans a new photoresist and high purity chemicals complex near Seoul, Adeka is upgrading equipment for advanced semiconductor chemicals, and wafer makers Shin-Etsu Chemical and SUMCO are preparing substrates for increasingly strict manufacturing requirements.

As of November 2, 2025, those investments serve two markets: leading overseas foundries preparing advanced chips and a growing manufacturing base inside Japan. Rapidus began pilot production in Chitose, Hokkaido, in April 2025 and targets mass production in 2027. The Japanese government has pledged more than 1.7 trillion yen in support, making the project an anchor for suppliers seeking domestic customers.

Artificial intelligence, high performance computing and advanced automotive systems are driving demand for the new chips. Smaller, more efficient circuitry can help processors carry out demanding tasks while controlling power use. Making that circuitry reliably requires wafers, light sensitive coatings, solvents, gases, adhesives and resins with tighter tolerances, higher purity and greater uniformity than previous generations.

Japanese suppliers, long trusted for quality and precision, see an opportunity across both chip fabrication and packaging. Fabrication builds the electronic circuits on a silicon wafer. Packaging connects the finished chips to other components and protects them. At 2 nm, shortcomings in either stage can affect performance, production yields and reliability.

TSMC, Samsung and Intel are pushing new manufacturing nodes, while Rapidus aims to bring 2 nm production to Japan within this decade. A node describes a generation of chipmaking technology. Suppliers must match the requirements of each customer's process while delivering consistent materials in large quantities.

Why 2 nm changes the materials requirements

Leading chipmakers are adopting gate all around transistors, known as GAA, and more complex chip architectures at 2 nm. A transistor acts as a tiny electrical switch. In a GAA design, the gate wraps around nanosheets or nanowires, improving control over the current flowing through them.

Better control helps reduce leakage, the electricity that escapes when a transistor should be switched off. It also helps limit power use at very small scales. Producing these structures requires carefully selected high-k dielectrics, metal gates and metals used to tune the work function, which helps determine the voltage needed to operate a transistor. High-k dielectrics provide electrical insulation while supporting the gate's control.

Trace contamination can change threshold voltages, the points at which transistors switch on, or create paths for leakage. Cleanroom conditions and the purity of every chemical therefore become part of the device's performance. A material that varies from one delivery to the next can make an already demanding process harder to control.

Manufacturers also need extremely flat silicon wafers, specialized packaging materials and resist chemistries for extreme ultraviolet lithography, or EUV. Lithography uses light to transfer patterns onto a wafer. Each manufacturing step has a narrow range of conditions in which it works properly, so reliable materials are essential to yield, the share of production that results in usable chips.

Photoresists and chemicals move closer to customers

Tokyo Ohka Kogyo, a global leader in photoresists, plans a site near Seoul with an EUV resist plant and a high purity chemicals factory. Photoresist is a light sensitive coating that allows chipmakers to form intricate patterns. Locating production near major foundries supports rapid trials, process adjustments and delivery.

EUV uses light with a very short wavelength. The resist must respond sensitively while keeping the edges of printed lines smooth and contamination low. At 2 nm, formulation and treatments after application become increasingly demanding because small variations can affect delicate features.

Suppliers are also increasing capacity for developers, strippers and cleaning chemicals. Developers help reveal the intended pattern, while strippers remove resist when it is no longer needed. Rinsing and cleaning must be controlled closely because an extra rinse or traces of metal can affect device performance.

Adeka's equipment upgrades target advanced semiconductor chemicals. Together with investment in photoresists and related products, these moves reflect a wider effort to serve the first wave of overseas 2 nm production while preparing for demand from Rapidus and other Japanese projects.

EUV processing brings further challenges. Patterns at 2 nm require more complex steps involving multiple patterning operations, while upcoming EUV tools with high numerical aperture will push resolution further. Numerical aperture describes a property of an optical system that helps determine how finely it can resolve a pattern.

Photoresist developers must balance sensitivity, resolution and edge roughness while reducing stochastic defects, small random flaws that can occur during pattern formation. Bake conditions after exposure and defect inspection also need careful control. Solvents and rinses surrounding the resist must avoid etching or swelling the fragile structures.

Wafers, polishing materials and gases face tighter limits

Shin-Etsu Chemical and SUMCO together supply a large share of the world's silicon wafers measuring 300 millimeters across. Their wafers provide the surface on which advanced circuits are built, making flatness, particle control and crystal quality central to accurate patterning.

Both companies are tuning substrates for the tighter flatness requirements and lower defect densities needed at 2 nm. These improvements matter for patterning on the front of the wafer and for processes being studied on its back. A small surface irregularity can make precision work across the wafer more difficult.

Chemical mechanical polishing slurries are evolving alongside the wafers. These mixtures help smooth surfaces through a combination of chemical action and mechanical polishing. Denser circuit patterns require uniform removal rates so that one area is not polished more heavily than another.

Specialty gases used for deposition and etching also require tighter purity. Deposition adds thin layers of material, while etching removes selected material to form structures. Unwanted interactions during either step can disturb GAA devices. The challenge extends across the production chain, from the starting wafer to the chemicals and gases used repeatedly during fabrication.

Packaging becomes part of the performance equation

AI accelerators combine computing chips with stacks of high bandwidth memory to move large amounts of data quickly. As chip power and memory needs rise, packaging becomes a central design decision. It must hold increasingly dense assemblies together, connect their components and help remove heat.

Ajinomoto Fine-Techno, known for ABF build-up films, Resonac, Nissan Chemical, Sumitomo Bakelite and Namics are expanding work in packaging materials. Their areas include underfills, encapsulants, temporary bonding adhesives and resins that control warpage. Underfills support connections beneath chips, encapsulants protect components, and temporary adhesives hold parts in place during manufacturing.

Warpage is bending caused by stresses in an assembly, including those associated with temperature changes. Keeping components flat and aligned matters when electrical connections are extremely small and closely spaced. Die attach films and thermal interface materials also help secure chips and transfer heat away from them.

Manufacturers use 2.5D and 3D packaging techniques to place components beside one another or in stacked arrangements. Interposers provide connections between components, while microbumps, copper pillars and through-silicon vias carry signals through dense assemblies. Each approach places different demands on adhesives, resins and other materials.

The JOINT2 collaboration brings materials specialists together with Rapidus and Japan's Leading-Edge Semiconductor Technology Center to work on 3D packaging processes. Its work includes keeping chips aligned and thermally stable. Precision tools from Japanese equipment makers support these efforts, linking materials development with the engineering needed to assemble chips reliably.

Packaging compounds must withstand repeated heating and cooling and remain reliable over long service lives. They control stress, limit bending and move heat out of tightly packed systems. Achieving the performance sought from 2 nm chips therefore depends on the package as well as the circuitry inside it.

Rapidus anchors Japan's domestic ambition

Rapidus sits at the center of Japan's effort to produce 2 nm chips domestically. After beginning pilot production in April 2025, the company demonstrated core elements of 2 nm GAA devices with partners. It aims to provide customer samples after prototype runs and move to mass production in 2027.

Rapidus President Atsuyoshi Koike has identified production yield and reliability as major challenges in turning development work into stable output at high volumes.

Developing mass production technology is extremely difficult, with confirming yields and ensuring reliability as major obstacles.

The government has pledged more than 1.7 trillion yen in support and created new mechanisms for investment and loan guarantees. Policymakers have also sought safeguards tied to public funding, including conditions intended to protect key technology and corporate governance. Building the full production system will require public support and private investment over several years.

Rapidus is intended to support a wider network of companies through joint development in materials, metrology, lithography and packaging. Metrology means measuring structures and process results with enough precision to identify manufacturing problems. Without a domestic anchor for advanced logic production, equipment and materials suppliers face a stronger pull to move capacity abroad toward their customers.

The company is experimenting with a processing flow involving single wafers or batches to accelerate feedback and shorten learning cycles. It is also pursuing an integrated approach to fabrication and packaging, seeking faster customer turnarounds in niche markets. Engineers have been sent to partner laboratories to learn advanced processes, alongside recruitment in Japan and overseas.

Overseas chipmakers deepen their presence in Japan

TSMC's subsidiary in Kumamoto is expanding with a second plant, increasing regional demand for wafers, chemicals and photoresists. Local procurement can shorten delivery times and improve quality control, both valuable when a factory is bringing a new manufacturing process into operation.

Samsung plans an advanced packaging research center in Yokohama to improve connections between processors and memory for AI workloads. The center will coordinate with Japanese materials and equipment suppliers and universities, linking research with pilot lines and commercial manufacturing processes.

For Namics, Resonac and other packaging specialists, proximity to a major customer's research and development program creates opportunities to develop underfills, die attach films and resins with low warpage together. Materials can be adjusted in response to the customer's actual assembly requirements.

These investments strengthen Japan as a hub for advanced materials while core 2 nm wafer production develops across several regions. Global foundries continue to depend on Japanese wafers, photoresists and other consumables. Overseas demand and new domestic operations give suppliers a broader customer base.

Milestones from pilot production to mass output

Rapidus provides the clearest sequence of dated milestones in Japan's domestic 2 nm effort. Suppliers are preparing for that schedule while also serving overseas chipmakers advancing their own nodes.

• April 2025: Rapidus began pilot production in Chitose, Hokkaido.
• By November 2, 2025: Rapidus had demonstrated core elements of 2 nm GAA devices with partners and planned customer samples after prototype runs.
• 2027: Rapidus targets the start of mass production.
• 2030: Japan's targets for domestic semiconductor sales assume progress in both overseas supply opportunities and production at home.

No opening date was given for Tokyo Ohka Kogyo's planned complex near Seoul or Samsung's planned packaging research center in Yokohama. Progress at those projects, TSMC's Kumamoto expansion and Rapidus will help show how quickly demand for Japanese materials develops.

What the changes mean for AI, vehicles and energy use

AI training and inference, the use of a trained model to produce answers or predictions, are pushing data centers toward their power and cooling limits. Chips made with 2 nm technology, combined with advanced packaging and high bandwidth memory, aim to deliver more computation for each watt of electricity.

Better efficiency could reduce energy bills and carbon footprints for cloud operators while supporting larger models and faster inference. In devices outside data centers, it could enable more intelligence within robots, industrial systems, wearables and household electronics rather than relying entirely on remote computing.

Automotive companies need dependable processors for driver assistance and future autonomous functions. Their chips must also withstand temperature swings and operate over long product lifecycles. Packaging and interconnect materials play a central role in meeting those reliability requirements.

Japanese automakers and electronics companies are watching the 2 nm effort because access to advanced domestic logic production could speed joint design work and shorten supply lines. Communications, healthcare and defense also have an interest in reliable access to computing capacity. Production in more than one region gives system makers more sourcing options, while Japan's materials expertise gives it a strong position within that network.

Costs, staffing and production consistency shape the expansion

New manufacturing nodes often face unstable yields, limited supplies of key equipment and pressure on costs. EUV tools with high numerical aperture and the resist layers used with them need stable production recipes. Competition for skilled engineers adds another constraint across the industry.

Materials companies are building teams near customer factories in Japan and Korea to support rapid trials and process adjustments at those sites. They are also placing production capacity close to customers for quick delivery timed to manufacturing needs. These arrangements help suppliers respond when a customer changes a process or identifies a defect.

Investment extends to greener chemistries, reclaim systems and water treatment to meet environmental standards. Companies are deepening research partnerships with universities and research centers to accelerate changes in EUV resist formulations, films with low dielectric constants and packaging compounds that conduct heat. Some are considering joint ventures to share the risk of expensive plants.

Chinese foundries expanding at mature nodes may affect materials pricing and supply patterns. At advanced nodes, TSMC, Samsung and Intel will set process requirements that suppliers must meet. Consistent quality at scale, together with the ability to reduce defects and variation, will influence which materials companies gain business.

Japan's materials strategy reaches beyond a single factory

Japan is seeking to rebuild its semiconductor position through areas where it is already strong, especially materials and equipment. Expansion by Tokyo Ohka Kogyo, Adeka, Shin-Etsu Chemical, SUMCO, Ajinomoto Fine-Techno, Resonac, Namics and other companies supports that strategy. Research alliances and subsidies are intended to help close gaps as suppliers serve overseas factories and new capacity at home.

Milestones to watch include the maturity of Rapidus prototypes and early customer engagements, new shipments of EUV resists and high purity chemicals for tools with high numerical aperture, and progress in 3D packaging resins and adhesives through JOINT2. Construction at TSMC's Kumamoto expansion and Samsung's Yokohama packaging site will also indicate demand for local materials and tools.

Japan's role in 2 nm manufacturing depends on the reliability of the full materials network rather than one factory alone. Wafers, fabrication chemicals and packaging compounds must work consistently together. Suppliers that maintain quality and develop products alongside customers have an opportunity to become essential partners in the next generation of chipmaking.

Key Points

• Japanese materials suppliers are expanding to serve overseas 2 nm chipmakers and new manufacturing projects in Japan.
• Tokyo Ohka Kogyo plans EUV resist and high purity chemicals production near Seoul, while Adeka is upgrading equipment.
• Shin-Etsu Chemical and SUMCO are improving wafers for tighter flatness and defect requirements.
• Packaging specialists are developing adhesives, underfills and resins for dense computing and memory assemblies.
• Rapidus began pilot production in April 2025 and targets mass production in 2027, backed by more than 1.7 trillion yen in pledged government support.
• TSMC's Kumamoto expansion and Samsung's planned Yokohama research center increase opportunities for Japanese suppliers.
• Yield, reliability, equipment availability, staffing and funding remain central challenges.