Micron Rejects 4F² DRAM, Bets on Wafer Bonding and 3D Memory as Rivals Take Another Route

Micron sets a different course for the next decade of memory

Micron Technology will keep developing its existing 6F² DRAM cell structure rather than adopt the smaller 4F² design being pursued by Samsung Electronics, SK Hynix and China's ChangXin Memory Technologies (CXMT). Its alternative combines further improvements to conventional DRAM, wafer bonding and eventual development of 3D DRAM.

At its October 21, 2026, technology webinar, Micron put a firm date on the next major step: volume production of 1-delta DRAM in Boise, Idaho, in the second half of 2027. The company targets an increase in bit density in the mid 20% range compared with its current 1-gamma generation, meaning more stored data in the same chip area.

Scott DeBoer, Micron's president and chief technology and products officer, said the company sees fundamental physical problems with further scaling of 4F². Micron's presentation said it had studied the architecture for more than 20 years and found no viable scaling path.

Samsung and SK Hynix are taking a different route. Both are researching vertical transistor structures intended to make 4F² practical before a later transition to 3D DRAM. CXMT is also pursuing the design for server memory while facing restrictions on access to advanced chipmaking equipment.

The competition turns on a practical question: which approach can deliver more reliable memory at a lower cost? Micron is betting that extending a familiar cell design while changing how chips are built and connected will serve customers better than moving to 4F².

Why a smaller cell creates a bigger argument

DRAM is the working memory that holds information a computer needs quickly. Each conventional memory cell stores one bit of data using a transistor, which acts as a switch, and a capacitor, which holds an electrical charge.

The labels 6F² and 4F² describe a cell's footprint relative to a manufacturing dimension called F. At the same F, moving from six units of area to four would cut the nominal cell footprint by one third. In an ideal layout, that would allow 50% more cells in the same area, because six divided by four is 1.5.

Micron's objection centers on the capacitor. Even when a transistor stands vertically to occupy less space, the capacitors above it still need enough room to remain stable, retain charge and avoid interference with their neighbors. DeBoer said capacitor pitch, the spacing between capacitors, is the foundational limit on DRAM bit density.

DeBoer explained Micron's reasoning during the question and answer session:

There's fundamental problems with 4F² scaling, that ultimately will lead to 3D DRAM coming in instead of 4F².

Manufacturing adds further constraints. Taller, narrower structures are harder to form consistently, while thinner electrical connections can have higher resistance and slow the movement of signals. The commercial benefit depends on how many working bits emerge from a wafer after these difficulties are addressed.

What Micron plans to build, and when

Micron says its 1-gamma technology is already in high volume manufacturing and will underpin products introduced over the following 12 months. Its next generation, 1-delta, is intended to support products including HBM5, vertical HBM and memory for AI inference close to the device using it.

The subsequent 1-epsilon generation brings wafer bonding into the DRAM roadmap. This process allows separately manufactured wafers to be joined, giving engineers more freedom to build memory cells and their supporting circuits using different manufacturing steps.

Micron also identifies High-NA EUV lithography and new materials as tools for later generations. High-NA EUV uses an advanced optical system to print finer chip patterns. Alongside that work, the roadmap includes two stages of 3D DRAM development, labeled 3D1 and 3D2.

• October 21, 2026: Micron outlines its decision to extend 6F² and develop wafer bonding and 3D DRAM.
• Second half of 2027: Micron targets volume production of 1-delta DRAM in Boise.
• Second half of 2027: Generation 11 NAND is also scheduled to begin its production ramp.
• Later DRAM generations: 1-epsilon introduces wafer bonding, followed by work on advanced lithography, new materials and 3D DRAM.
• 2027 through 2030: Micron's HBM roadmap runs through HBM4E, HBM5, HBM5E and HBM6 in successive years.

Micron gave no firm commercial launch date for 3D DRAM. DeBoer said the transition will depend on cost, manufacturing complexity and device performance, while expressing confidence in several more generations of conventional planar DRAM development.

Samsung and SK Hynix pursue vertical transistors

Samsung's approach combines vertical channel transistors, wafer bonding and research into an oxide semiconductor called indium gallium zinc oxide, or IGZO. Its advanced 4F² research has been under way for about five years.

IGZO is being investigated to reduce leakage current, the unwanted escape of electrical charge. Leakage matters because a DRAM cell must hold its charge long enough for the computer to read it reliably. Samsung's bonding concept separates the wafer containing memory cells from the wafer containing supporting circuits, then joins them.

SK Hynix has disclosed research combining a 4F² vertical gate platform with wafer bonding. Its strategy uses that architecture to pursue greater density and lower power consumption while also preparing for 3D DRAM over the longer term.

Industry projections place potential Korean 4F² production around 2027 to 2028, although more cautious estimates put meaningful output from the established suppliers in late 2028 or later. Those projections depend on development, customer qualification and production yield, the share of manufactured chips that work correctly.

Wafer bonding is therefore a shared tool across competing strategies. Samsung and SK Hynix aim to use it to help make 4F² practical. Micron plans to use it while retaining 6F². The disagreement concerns the cell architecture and the order of development, rather than whether bonding has a role.

CXMT seeks a route around equipment restrictions

CXMT's interest in 4F² has another driver: restrictions on access to extreme ultraviolet lithography equipment. The company is pursuing a structural change that could raise density while using older argon fluoride lithography tools.

Its proposed approach combines vertical gate structures with hybrid bonding across wafers measuring 12 inches in diameter. Memory arrays and peripheral logic circuits are made separately and then connected. Estimates associated with this approach suggest a potential increase in storage density of 30% to 50%.

CXMT is targeting DDR5 registered memory modules, known as RDIMMs, for servers. Its announced goal is a product introduction before the end of 2026, with customer qualification also targeted within the year. Production yield, shipment volumes and the schedule for a broad commercial ramp have not been disclosed.

That leaves several steps between the announcement and a substantial increase in market supply. Server customers must qualify the memory, and CXMT must manufacture it consistently at a cost that supports larger shipments.

Goldman Sachs forecasts CXMT's monthly DRAM wafer capacity rising from 290,000 at the end of 2026 to 513,000 at the end of 2028. That is an increase of 223,000 wafers, or about 77%. The bank also estimates that CXMT could meet about 50% of China's DRAM demand and 40% of its HBM demand by 2028.

HBM adds requirements beyond manufacturing the memory cells. It also needs advanced packaging, reliable connections through stacked chips and a capable base logic die. Access to the necessary equipment and manufacturing processes will help determine how quickly CXMT can expand across different memory markets.

Vertical HBM puts memory directly above the processor

Micron's vertical HBM proposal changes where memory sits in an AI system. Conventional HBM already stacks multiple DRAM chips, but that stack normally sits beside the processor on an interposer, a connecting platform that carries signals between components.

Vertical HBM places the memory directly on top of the processor. Micron plans to use hybrid bonding, which joins extremely closely spaced contacts, to create a shorter and denser set of connections between memory and computing hardware.

The main goal is greater bandwidth, meaning more data transferred each second. AI processors repeatedly move large amounts of information between memory and computing circuits. Faster connections can help the processor spend more time calculating and less time waiting for data.

Heat makes the design difficult. A powerful processor generates substantial heat, and memory placed above it must operate reliably in that environment. DeBoer said bandwidth is the main driver of vertical HBM, while memory capacity will advance at a different pace because of thermal constraints.

Micron is developing heat management approaches, including heat spreaders over hotter parts of an HBM base die. It is also working on vertical edge inference memory, or vEIM, with an initial bandwidth target of about 2 terabytes per second per module. Edge inference means running an AI model near where data is collected or used.

Micron's plans cover several different kinds of vertical construction: bonding wafers, stacking memory chips above a processor, and eventually building 3D DRAM cell structures. Each addresses a different part of the problem of fitting more memory and faster connections into a limited space.

Annual HBM advances meet tight supply

Micron's product roadmap places HBM4 in 2026, HBM4E in 2027, HBM5 in 2028, HBM5E in 2029 and HBM6 in 2030. The schedule sets out the company's intended annual product progression, with standard and customized products developed alongside emerging vertical designs.

Micron says its current HBM4 is already in high volume manufacturing. A stack containing 12 memory dies provides 36 gigabytes of capacity and more than 2.8 terabytes per second of bandwidth, with speeds above 11 gigabits per second on each pin.

The company claims more than 20% better power efficiency than HBM3E. It is also sampling a version containing 16 memory dies and 48 gigabytes of capacity. Customized products are expected to place customer specific memory and logic functions in the base die, while standard products remain part of the range.

Micron says its 2026 HBM supply was sold out. Chief executive Sanjay Mehrotra expects supply to remain tighter than demand through 2027 and 2028, while additional packaging capacity in Singapore is expected to contribute in the first half of 2027.

These supply constraints matter for buyers planning AI systems. More memory bandwidth can improve system performance, but customers also need predictable delivery, manageable power use and enough capacity for their workloads. Micron is trying to address those requirements together through closer product development with customers.

The same roadmap reaches phones, servers and storage

Micron's plans extend beyond HBM. The company projects about 35% better power performance for LPDDR6 than LPDDR5, with larger improvements at some capacities. LPDDR memory is used in mobile devices and is also attracting data center interest because of its power characteristics.

DDR6 is intended to deliver about twice the bandwidth of DDR5. Micron also plans a server RDIMM with 1 terabyte of capacity, following its recently sampled module holding 512 gigabytes. Larger modules allow servers to hold more information in working memory.

For NAND flash, which retains stored data when power is switched off, Micron targets a Generation 11 production ramp in the second half of 2027. The design uses wafer bonding and more than 400 layers. Micron says it will more than double bit density compared with Generation 9, target 1.5 times the input and output speed, and reduce data transfer energy per bit by more than 25%.

Chinese competition is also expanding in NAND. Omdia figures put Yangtze Memory Technologies at 14.2% of the global NAND market in the second quarter, compared with Samsung at 28.1%. Within China, YMTC held 38.7%, ahead of Samsung's 33.4%. NAND has used vertical cell stacking for years, while DRAM faces a more difficult transition because of its cell design.

Working chips and production costs will decide the contest

Micron's choice shifts engineering effort toward extending 6F², improving bonding and preparing 3D structures. Samsung, SK Hynix and CXMT are spending effort on making a smaller cell architecture work reliably. Both routes carry manufacturing risks.

For 4F², the challenges include capacitor spacing, leakage, narrow electrical connections and controlling charge inside vertical transistors. Bonding adds exacting alignment requirements. The financial reward depends on producing enough working memory to offset the extra process steps and development costs.

Equipment suppliers face changing requirements under either strategy. Atomic layer deposition places extremely thin coatings on structures, while etching removes material to form narrow, deep features. Both become important as memory structures grow taller and more complex.

Investors have reacted sharply to the competing prospects of tight supply and future Chinese expansion. On October 16, Micron shares fell more than 3% and SK Hynix more than 5% amid concern about CXMT's progress. Samsung and SK Hynix later rose about 6% in South Korean trading on October 21, illustrating how quickly expectations have shifted.

Customers face a more immediate concern: how much memory will be available for their products. KeyBanc analyst John Vinh forecasts that a shift of capacity toward data centers could reduce memory supply for PCs and smartphones by 20% to 30% in 2027. His price forecasts include DRAM increases of 15% to 20% in the fourth quarter of 2026 and NAND increases of about 20%.

The next concrete milestones are CXMT's planned server memory introduction before the end of 2026, Micron's additional packaging contribution in early 2027, and its 1-delta and Generation 11 NAND ramps in the second half of 2027. Customer qualification, working chip output and manufacturing cost will show how the competing plans translate into products.

Key Points

• Micron has rejected 4F² DRAM in favor of extending 6F², adding wafer bonding and developing 3D DRAM.
• Its 1-delta DRAM is scheduled for volume production in Boise in the second half of 2027, targeting a density gain in the mid 20% range.
• Samsung and SK Hynix are researching 4F² vertical transistor structures alongside bonding and longer term 3D DRAM work.
• CXMT targets a 4F² server memory introduction before the end of 2026; its production scale remains undisclosed.
• Vertical HBM would place memory directly above processors to increase bandwidth, with heat management a central challenge.
• Micron plans successive HBM generations through 2030 and expects memory supply to remain tight through 2027 and 2028.