TSMC Plans 3nm Chip Production in Japan as Kumamoto Investment Is Reported at $17 Billion

Kumamoto Moves Into Advanced Chip Manufacturing

Taiwan Semiconductor Manufacturing Company (TSMC) has confirmed plans to make advanced 3 nanometre chips at its second factory in Kumamoto, southern Japan, upgrading a project previously intended to manufacture chips using processes ranging from 6 to 12 nanometres. The investment is reported to reach about $17 billion, compared with the $12.2 billion originally allocated to the facility.

Chief Executive Officer CC Wei announced the decision during a meeting with Japanese Prime Minister Sanae Takaichi in Tokyo. As of February 6, 2026, TSMC has confirmed the change in manufacturing technology but has declined to verify the reported investment figure.

The upgrade would put Japan alongside Taiwan and the United States in TSMC's plans for advanced manufacturing. TSMC currently makes its 3nm chips exclusively in Taiwan and plans to begin producing them at its second Arizona factory in 2027. Kumamoto would give customers another location for obtaining chips used in demanding computing applications.

Artificial intelligence is a central reason for the expansion. TSMC manufactures chips for companies including Nvidia, whose processors support the growing demand for AI computing. The Japanese project connects that commercial demand with Tokyo's effort to rebuild domestic semiconductor production and protect supplies for important industries.

Construction of the second Kumamoto factory has already begun. The project operates through Japan Advanced Semiconductor Manufacturing (JASM), a joint venture involving Sony and other Japanese stakeholders. TSMC's first Kumamoto facility began operations in February 2024 and focuses on established manufacturing processes. The second would bring a much more advanced production capability to the same region.

Wei, TSMC's chief executive, described the planned factory's importance for Japan's economy and AI industry during his meeting with Takaichi:

We believe this fab will further contribute to the local economic growth and, most importantly, form a foundation for Japan's AI business.

What the Reported $17 Billion Would Mean

The reported $17 billion investment would be $4.8 billion more than the original $12.2 billion budget for the second facility, an increase of about 39%. That comparison shows the scale of the proposed expansion in spending as the project shifts to a more advanced manufacturing process.

TSMC's confirmation concerns the move to 3nm production. The company has left the specific investment amount unconfirmed, while Japan is reportedly considering further financial support for the upgraded project. Tokyo has already provided substantial subsidies for TSMC's first facility in Kyushu, the island where Kumamoto is located.

JASM gives TSMC a local partnership through which to develop its Japanese operations. Sony brings an established semiconductor business and experience working within Japan's industrial and regulatory environment. Other Japanese stakeholders also participate in the venture.

Wei thanked Japan's central government, the Kumamoto Prefectural Government and local communities for supporting the project. Their involvement matters because a semiconductor factory, often called a fab, needs more than a building and production machinery. It also depends on a network of suppliers, transport connections and local coordination.

TSMC has tied the final production arrangements to demand and business conditions. In its statement about the second plant, the company said:

the technologies and ramp schedule will be based on our customers' need and market conditions.

A ramp schedule is the process of bringing a factory into production and gradually increasing its output. The company's wording leaves room to adjust how quickly the facility starts making chips and reaches larger production volumes.

Why the Move From 6nm to 3nm Matters

The second Kumamoto factory was originally planned around processes ranging from 6nm to 12nm. Those technologies serve applications including automotive electronics, consumer devices and general computing. Moving to 3nm changes the kind of demanding work the facility can support.

A nanometre is a very small unit of length used in the names of semiconductor manufacturing processes. In this project, the move to a smaller process generation means the ability to fit more transistors into a smaller space while improving performance and power efficiency. Transistors are the tiny electronic switches that allow a chip to process information.

Three nanometre technology can pack billions more transistors into compact chips. That capability is valuable for high performance computing systems and AI servers, where processors must carry out enormous numbers of calculations. The applications described for these advanced chips range from autonomous vehicles to cloud data centers.

AI models require computing power both while they are being trained and while they are answering requests or carrying out tasks. Training teaches a model from data; running it uses that training to produce a result. Faster, more efficient chips help with both stages.

The demand for computation associated with large AI models can double roughly every few months. Electricity consumption is also a major operating cost. These pressures help explain why chip designers seek manufacturing processes that deliver greater processing speed while using energy more efficiently.

Six nanometre chips remain useful for many consumer electronics and automotive applications. The Kumamoto upgrade responds to a different set of requirements: the intense computing workloads of AI accelerators and other advanced processors. It gives the second plant a larger role in the commercial push to expand AI capacity.

Japan Makes Chips a National Priority

Japan's government has positioned semiconductor manufacturing as a national project intended to keep the country strategically important in technology competition between major powers. Takaichi described 3nm chips as having great significance for economic security.

Economic security, in this case, means maintaining reliable access to technologies needed by industries such as electronics, vehicle manufacturing and defense. A disruption in chip supplies can affect many businesses at once, which gives semiconductor production a role beyond the fortunes of a single company.

An analysis by the Brookings Institution puts Japan's investment in rebuilding its semiconductor sector between 2022 and 2025 at roughly $25.7 billion, equivalent to about 0.71% of its gross domestic product. GDP measures the value of goods and services produced in an economy.

The same comparison gives semiconductor investment equivalent to 0.41% of GDP for Germany, 0.21% for the United States and 0.2% for France. Japan's 0.71% is more than three times the US share of 0.21%, showing how heavily Tokyo has committed relative to the size of its economy.

Japan's Ministry of Economy, Trade and Industry began talks to attract TSMC investment in 2019. Those discussions preceded the pandemic and the global chip shortages that later exposed vulnerabilities in manufacturing concentrated in a small number of locations.

Government subsidies support a policy aimed at reducing exposure to supply disruptions. The upgraded Kumamoto plan extends that effort from established chip processes toward the advanced processors increasingly sought by AI businesses.

Rapidus Pursues a Different Technology Route

Japan is also backing Rapidus, a domestic semiconductor foundry venture that aims to manufacture 2 nanometre chips in Hokkaido by 2027. A foundry makes chips designed by other companies. Japan's government has determined that Rapidus and TSMC's Japanese operations will serve different markets and applications rather than compete directly.

The two projects use different transistor designs. TSMC's planned 3nm production relies on proven Fin Field Effect Transistor (FinFET) technology, while Rapidus intends to move directly to Gate All Around (GAA) architecture for its 2nm process.

Both designs concern how a transistor controls the flow of electricity. FinFET uses a structure shaped like a fin, while GAA places the controlling gate around the channel through which current travels. The difference gives the projects separate technical routes toward efficient, powerful chips.

TSMC's Kumamoto plant is intended to address immediate commercial demand for AI processors through established technology suitable for production in large volumes. Rapidus is targeting a future generation of high performance computing and military applications requiring advanced energy efficiency and radiation tolerance. Radiation tolerance means the ability of electronics to keep working when exposed to radiation.

The Brookings analysis describes Japan's approach as a hedge: combining a TSMC partnership with relatively low risk and high certainty with a Rapidus venture carrying higher risk and potentially higher returns. TSMC brings an established manufacturing business, while Rapidus represents Japan's ambition to develop advanced domestic capabilities.

The practical benefit for Japan is a combination of near term industrial activity and a more ambitious technology effort. Investment around TSMC can rebuild parts of the semiconductor ecosystem while Rapidus works toward its separate production target.

Arizona and Kumamoto Expand TSMC's Reach

TSMC's Japanese upgrade forms part of a much larger expansion beyond Taiwan. In March 2025, the company announced plans to increase its investment in the United States to $165 billion, including three new fabrication plants and two advanced packaging facilities in Arizona.

The second Arizona fab is scheduled to begin installing tools for 3nm production in the summer of 2026, with volume production targeted for 2027. A similar timeframe is envisioned for the upgraded Japanese facility, although TSMC has made Kumamoto's production schedule dependent on customer needs and market conditions.

Taiwan remains the current location for TSMC's 3nm manufacturing. Adding capacity in Arizona and Kumamoto would distribute production across three political jurisdictions, giving customers more geographic options for obtaining advanced chips.

Apple, Nvidia, AMD and Qualcomm are among the major customers associated with TSMC's advanced manufacturing business. Their products depend on reliable production, making the location of factories an important part of supply planning.

Geographic diversification gives TSMC alternatives when regional conflict, trade disputes or natural disasters disrupt manufacturing. The purpose is to reduce dependence on a concentration of production in Taiwan while expanding capacity to meet demand.

TSMC's American Depositary Receipts, securities traded in the United States that represent shares in the company, rose 0.77% before the market opened following the Japanese announcement. The increase reflected an immediate positive investor response to the expansion plan.

Japan's Suppliers Give the Project a Local Base

Japan already holds strong positions in equipment and materials needed to make semiconductors. Its companies account for an 88% global market share in coater developers and 53% in silicon wafers. Coater developers handle coating and developing steps during chip production, while silicon wafers provide the base on which chips are made.

Tokyo Electron, Shin Etsu Chemical and Ibiden are among the Japanese suppliers providing essential manufacturing equipment, materials and packaging substrates. A substrate is a supporting base used to connect and package a chip.

TSMC has reportedly set a target of sourcing 60% of procurement locally for its Kumamoto operations. Meeting that target would spread spending beyond the factory itself to businesses supplying the materials, equipment and other inputs needed to run it.

Japan's existing supplier network helps explain why Kumamoto is attractive beyond the availability of subsidies. Advanced chip production needs specialized inputs, and proximity to experienced suppliers provides a practical foundation for the investment.

Sony supplied another specific commercial reason for TSMC's initial move into Japan: the opportunity to develop the next generation of CMOS image sensors together. These sensors convert light into electronic information used to produce images.

The Brookings analysis identifies that collaboration as a business opportunity supporting the geographic expansion. Sony's role as a major local partner also helped TSMC navigate complex regulatory processes. The partnership therefore connects a particular product opportunity with the practical work of establishing manufacturing in Japan.

Packaging Connects Chip Production to AI Demand

Advanced packaging is another part of the supply chain supporting AI processors. Manufacturing creates the chip, while packaging protects it and provides the connections needed for it to work with other components.

TSMC uses Chip on Wafer on Substrate (CoWoS) extensively for AI chip production. This packaging technology makes the supply of suitable substrates and related materials important alongside the production of the processor itself.

Ajinomoto illustrates how specialized that network can be. Although widely associated with food products, the company is also a major producer of Ajinomoto Build Up Film (ABF), a resin used in chip packaging.

Demand from high performance computing applications has helped the market values of companies such as Ajinomoto triple. The connection shows how spending on advanced computing can reach suppliers whose best known businesses lie outside chip manufacturing.

Japan's materials and packaging companies give TSMC an industrial base that extends across several stages of production. The planned local procurement target connects the Kumamoto investment to that wider network, rather than limiting its economic effects to the workers and equipment inside the new fab.

Construction Progress Follows Earlier Delays

Physical work on the second Kumamoto plant has begun after earlier reports of delays. In the middle of 2025, construction at the site reportedly slowed as TSMC prioritized its large Arizona expansion.

Wei initially cited regional traffic concerns as a factor. Japan's government challenged that explanation, saying TSMC had not formally reported infrastructure issues. The disagreement formed part of the debate over the pace of the Japanese project before the latest confirmation of construction and the technology upgrade.

The main dates in the development of Japan's semiconductor plans and TSMC's expansion are:

• 2019: Japan's Ministry of Economy, Trade and Industry began talks to attract TSMC investment.
• February 2024: TSMC's first Kumamoto facility began operations using established chip processes.
• March 2025: TSMC announced plans to raise its US investment to $165 billion.
• Middle of 2025: Work on the second Kumamoto site reportedly slowed amid priorities surrounding the Arizona expansion.
• As of February 6, 2026: TSMC had confirmed the Kumamoto upgrade to 3nm production, with construction underway.
• Summer 2026: Installation of 3nm production tools is scheduled to begin at the second Arizona fab.
• 2027: Arizona targets volume production, Rapidus aims for 2nm production in Hokkaido, and a similar timeframe is envisioned for the upgraded Kumamoto facility.

What Kumamoto Stands to Gain

Kumamoto's location offers proximity to existing semiconductor clusters, strong support from both prefectural and national authorities, and relatively low earthquake risk compared with other Japanese regions. Those conditions support TSMC's effort to reproduce aspects of its Taiwanese manufacturing operations in Japan.

The upgrade also changes the economic opportunity around the second plant. A facility originally intended for chips used in automotive and general computing applications is now being directed toward the advanced processors sought by the AI industry. That shift reflects the rapid change in market demand over the past year.

Wei said TSMC was discussing further collaboration with Japanese customers and partners across several areas important to AI. Combined with procurement from local suppliers, those discussions connect the factory plan to Japan's wider ambitions in advanced computing.

Japan is pursuing several connected goals: securing chip supplies, attracting manufacturing investment, strengthening local equipment and materials businesses, and supporting a domestic route to more advanced technology through Rapidus. Kumamoto is the established international partnership within that effort, while Hokkaido hosts the more ambitious domestic manufacturing project.

The immediate development is TSMC's confirmed commitment to 3nm production in Kumamoto. The reported increase to $17 billion would make the second factory a larger investment than originally planned, while the company's customer driven scheduling will determine how quickly the new capacity becomes available.

At a Glance

• TSMC has confirmed plans to manufacture 3nm chips at its second Kumamoto factory, replacing the earlier plan for processes ranging from 6nm to 12nm.
• The investment is reported at about $17 billion, compared with an original $12.2 billion budget. TSMC has declined to confirm the new amount.
• CEO CC Wei announced the upgrade during a meeting with Prime Minister Sanae Takaichi in Tokyo.
• Construction has begun, and TSMC says technology choices and the production ramp will depend on customer needs and market conditions.
• The first Kumamoto facility began operations in February 2024. Japan has already provided substantial subsidies and is reportedly considering further support.
• TSMC currently produces 3nm chips in Taiwan and targets production at its second Arizona fab in 2027.
• Rapidus separately aims to manufacture 2nm chips in Hokkaido by 2027 using GAA technology.
• TSMC's reported target of 60% local procurement would connect Kumamoto's expansion to Japan's equipment, materials and packaging suppliers.